Circuits and Systems, 2015, 6, 103-111 Published Online April 2015 in SciRes. http://www.scirp.org/journal/cs http://dx.doi.org/10.4236/cs.2015.64011 How to cite this paper: Dadoria, A., Khare, K., Gupta, T.K. and Singh, R.P. (2015) A Novel High-Performance Lekage-Tolerant, Wide Fan-In Domino Logic Circuit in Deep-Submicron Technology. Circuits and Systems, 6, 103-111. http://dx.doi.org/10.4236/cs.2015.64011 A Novel High-Performance Lekage-Tolerant, Wide Fan-In Domino Logic Circuit in Deep-Submicron Technology Ajay Dadoria, Kavita Khare, T. K. Gupta, R. P. Singh Electronics & Communication Engineering, MANIT, Bhopal, India Email: ajaymanit0@gmail.com , Kavita_khare1@yahoo.co.in , taruniet@radiffmail.com , prof.rpsingh@gmail.com Received 4 February 2015; accepted 17 April 2015; published 21 April 2015 Copyright © 2015 by authors and Scientific Research Publishing Inc. This work is licensed under the Creative Commons Attribution International License (CC BY). http://creativecommons.org/licenses/by/4.0/ Abstract As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high perfor- mance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed cir- cuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit. Simulation is performed in BISM4 Cadence environment at 65 nm process technolo- gy, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27˚C with CL = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59% HSD, 19.138%, 44.25% DFD respectively. Keywords High Speed Integrated Circuit, Dynamic Logic Circuit, Unity Noise Gain (UNG), Domino Logic Circuit, Noise Immunity 1. Introduction As technology scales down power consumption is dominant in deep sub-micron technology. Power consumption