Central Processing Units for PLC implementation in Virtex-4 FPGA M. Chmiel*, J. Mocha**, E. Hrynkiewicz***, A. Milik**** Institute of Electronics, Silesian University of Technology, Gliwice * (e-mail: miroslaw.chmiel@polsl.pl), ** (e-mail:jan.mocha@polsl.pl) *** (e-mail:edward.hrynkiewicz@polsl.pl), **** (e-mail:adam.milik@polsl.pl) Abstract: The paper presents an approach to the design and construction of central processing units for programmable logic controllers implemented in a FPGA development platform. Presented units are optimised for minimum response- and throughput time. The CPU structure is based on bit-word architecture and two types of control data exchange methods: with handshaking – control data are passed through the two flip-flop units with acknowledgement; without handshaking – control data are passed through the dual port RAM. Third unit – simple one processor – built to compare with the above two. The paper presents specific timers/counters hardware construction solution. Additionally it presents implementation results which show how many FPGA circuit resources are used to implement presented units. Keywords: Programmable Logic Controller (PLC), Central Processing Unit, Throughput Time, Concurrent Programs, Field Programmable Logic Array (FPGA). 1. INTRODUCTION One of the main parameters (features) of Programmable Logic Controller (PLC) is scan time – execution time of one thousand control commands. Due to this fact designing and construction of the CPU should have an architecture that enables fast control program execution. It is a very important task. The most of developed CPUs of PLCs delivered by well-known manufacturers are constructed as multiprocessor units. Particular processor in such units executes the commissioned for it tasks. In this way one can obtain a unit, which make possible concurrent operation of a few processors. For such CPU the main problem to solve is the way of task assignment to particular processors and finding a structure of CPU be able to execute of such task assigned in practice as it was shown by (Michel, 1990). The other important problem inseparable from hardware are programmatic tools. Those tools should enable easy and efficient creation of control algorithm. The programming toolbox should take benefits from all aspects of multiprocessor unit. Apart from instruction execution time, the access time to internal (markers, counters, timers), and external (inputs and outputs) resources is a very important parameter. Another parameter which characterises PLC is throughput time. It is defined as the response time to the change of object signals. From the point of view of the object, this parameter is most important, which describes the quality of control that is directly derived from the central processing unit and programmatic toolbox (Chmiel, 2008). PLCs control mainly process of a binary nature. In some cases they are used for mixed control containing analogue signals (Koo et al., 1998). There are a lot of objects where control can form independent tasks. The boundaries of independent tasks are often determined by their analogue or binary nature, as well as process set of signals and control conditions. This observation leads to the conclusion: bit-word structure of PLC CPU well matches typical processed data. The CPU structure is oftentimes optimised for very fast logic operations and for execution of complicated arithmetic operation (including floating point). To benefit from described architecture both processors must work in parallel as independent as possible. To make it possible, two processors must be equipped with specific hardware and software solutions. The most effective and natural approach to the problem of task assignment is partitioning along the operation type (bit or word). The tasks operating on discrete input/outputs are executed by a bit-processor (Getko, 1983). Nowadays such processors may be implemented in programmable structures like CPLDs or FPGAs. It brings the positive effects in user program execution time (the controller speed-up). On the other hand a word-processor is built on the base of a standard microprocessor or embedded microcontroller. It is used for word data processing in control of analogue objects, numeric data processing and operating system maintenance of the PLC (networking, diagnostics, control loop) (Donandt, 1989; Aramaki et al., 1997). As it was mentioned above an efficient and most promising platform for control unit implementation is a platform based on programmable logic devices. This platform may be based on Field Programmable Logic (FPL), especially Field Programmable Gate Arrays (FPGAs). System architects are offered powerful tools which ensure acceptable financial and time outlays in comparison to effects. The FPL enables easy prototyping, testing and evaluating different solutions. Preprints of the 18th IFAC World Congress Milano (Italy) August 28 - September 2, 2011 Copyright by the International Federation of Automatic Control (IFAC) 7860