A FPGA-Based Bit-Word PLC CPUs Development Platform Miroslaw Chmiel*, Jan Mocha**, Edward Hrynkiewicz*** Silesian University of Technology, Institute of Electronics, Gliwice, Poland * (e-mail: miroslaw.chmel@polsl.pl) ** (e-mail: jan.mocha@polsl.pl) *** (e-mail:edward.hrynkiewicz@polsl.pl) Abstract: The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic controllers. Selected hardware solutions for the PLC dual processor bit-byte (word) CPUs, which are oriented for optimised maximum utilization of capabilities of the two-processor architecture of the CPU are presented in the paper. The key point is preserving high speed of instruction processing by the bit-processor, and high speed and functionality of the byte (word)-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimize the situations, when one processor has to wait for the other. Designed platform is based on the development board equipped with Xilinx Virtex-4 FPGA. Software tool for testing possibilities of the selected units and testing utilization of the programmable structure was also developed. Keywords: Programmable Logic Controller; Central Processing Unit; Bit-Byte (Word) Structure of CPU; Scan Time, Throughput Time, Concurrent Operation, Field Programmable Gate Array. 1. INTRODUCTION Entire operation cycle of a PLC (Programmable Logic Controller) consists of the following items: network communication, CPU test, object signal update and control program execution. Operations connected with object signal update and control program execution are considered in this paper. There are two typical architectures of a CPU known from literature that can be used. Those are: typical or slightly modified microcontroller (e.g. dedicated processors designed as ASICs - Application Specific Integrated Circuit or FPGA – Field Programmable Gate Array) and dual processor bit – byte (word) architecture with separated processing of instructions operating on binary and word data. There also exist very expensive multiprocessor solutions. Generally, computational possibility of the logic controller is defined as a time to execute thousand instructions (Getko, 1983; Modicon, 1990; Michel, 1990). The shorter time of instruction execution, the wider range of the applications that use logic controller. This is especially important for applications, which time constraints are high. Modern industrial objects require more and more complicated control devices. Of course this implies the need of applying control devices that enable of implementation of huge algorithms. Moreover, the implemented algorithm must be executed as fast as possible. The problem of developing of the central processing unit, which execute program in time as short as possibly, is still open (Donandt, 1989; Aramaki at al., 1997; Chmiel and Hrynkiewicz, 2005; Chmiel et al., 2005). This problem gained new platform for efficient and comfortable construct of the fast control units. This platform is based on the programmable logic devices (PLD), especially FPGAs. PLDs develop very dynamically. Designers have powerful tools which ensure acceptable financial and time outlays. PLDs enable easy prototyping and testing solutions on two stages: simulation and implementation. Besides the instruction execution time, very important parameter (or characteristic feature) is access time to internal resources: markers, counters, timers, and to external resources: inputs and outputs. Another parameter which characterizes PLC is throughput time defined as a response time on the change of the object signals. From the point of view of the object, this parameter is most important (Chmiel, 2008). All those parameters: the execution of thousand instructions, access time and throughput time are inextricably linked with each other. These parameters depend on each other and arise on each other. While working on the optimization of PLC central processing unit, all defined above parameters must be taken into account. Is must be noticed, that processes for which PLCs are applied have most of all binary character (strictly digital) or binary with small analogue component. Besides, there are also objects where analogue and digital parts are independent. This observation carry out to conclusion: it is possible to develop central processing units that in literature are called bit-byte (bit-word) – units with two processors for digital and analogue tasks. This structure is oftentimes optimized on very fast logic operations and on execution of the complicated arithmetic expressions. However, to make this possible, two processors must be equipped with specific hardware and software solutions. Firs of all both processors must work as independent as possible. This system must exploit