IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 6, JUNE 2008 707 Data Handling Limits of On-Chip Interconnects Rohit Singhal, Member, IEEE, Gwan Choi, Member, IEEE, and Rabi N. Mahapatra, Senior Member, IEEE Abstract—With shrinking feature size and growing integra- tion density in the deep sub-micrometer (DSM) technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They have large delays and are error-prone. Especially, in system-on-chip (SoC) designs, where parallel interconnects run over large distances, they pose difficult research and design problems. This paper presents a two-fold approach for evaluating the signal and data carrying capacity of on-chip interconnects. In the first approach, the wire is modeled as a linear time in- variant (LTI) system and a frequency response is studied. The second approach addresses delay and reliability in interconnects from an information theoretic perspective. Simulation results for an 8-bit-wide bus in 0.1- m technology are presented for both approaches. The results closely match to a similar optimal bus clock frequency that will result in the maximum data transfer rate. Moreover, this optimal frequency is higher than that achieved by present day designs which accommodate the worst case delays. The first approach achieves this higher transmission rate using ideal signal shapes, instead of square pulses, while the second approach uses coding techniques to eliminate high delay cases to generate a higher transmission rate. It is seen that the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using commu- nication theory, these “good” signals arriving early can be used to predict/correct the “few” signals that arrive late. I. INTRODUCTION R ECENT advances in the system-on-chip (SoC) tech- nology have given rise to complex communication systems between different modules on a chip. Even though the problems arising due to the size and magnitude of the logic have been alleviated by Moore’s law, the high speed data transfer over long distances poses difficult research problems. These long interconnecting wires are traditionally modeled as resistance–capacitance (RC) networks [1], [2]. More recently, with the high speed of switching, the inductive effects have become increasingly significant [3]–[6]. The most important problem that has been identified in long interconnects is of cross-talk, where adjacent signals interfere with each other resulting in not only errors and large delays, but also high energy consumption. In addition to cross-talk, the signal flowing through a wire is also affected by power noise and process variations [7]. Process variations result in imperfect wire dimensions, while power noise results in imperfect Manuscript received December 24, 2006; revised June 4, 2007. This work was supported by the National Science Foundation (NSF). R. Singhal is with the Department of Electrical Engineering Tech- nology, Texas A&M University, College Station, TX 77843 USA (e-mail: singhal@tamu.edu). G. Choi is with the Department of Electrical Engineering and Computer En- gineering, Texas A&M University, College Station, TX 77843 USA (e-mail: gchoi@ee.tamu.edu). R. N. Mahapatra is with the Department of Computer Science, Texas A&M University, College Station, TX 77843 USA (e-mail: rabi@cs.tamu.edu). Digital Object Identifier 10.1109/TVLSI.2008.2000255 Fig. 1. Schematics of buffer insertion and coding schemes. and ground values. Both result in errors at the receiver. While this paper includes the power noise as fluctuations in the driver voltages, it leaves out the effects of process variations as future work. Recent research has presented ideas to minimize the crosstalk effects through buffer insertion [8]–[10], coding [11]–[18], and other interesting techniques like variable cycle design [19] and wave-pipelining [20]. A coding technique to minimize the in- ductive crosstalk in off-chip interconnects has been presented in [21]. In [11], it is shown, using simulations, that coding is a better alternative to buffer insertion as it not only reduces wire-de- lays but also reduces the power consumption for data transmis- sion and improves reliability. Another important advantage of coding over repeater/buffer insertion that is missing in [11], is that buffers usually limit the dataflow in one direction, while coding allows the buses to operate in both directions as shown in Fig. 1. Previous works [22], [23] by the authors derives the Shannon’s Information Theoretic capacity [24], [25] of inter- connects. Reference [22] assumes only capacitive cross-talk, while [23] calculates the data capacity in the presence of both capacitive and inductive cross-talk and also power noise. Fur- ther, [23] also compares the codes proposed/discussed in [11] against this data capacity. In all existing communication channels, there exists a cutoff frequency after which the transmitted signal starts getting attenuated and below which all communication happens with minor losses. Intuitively, the on-chip interconnects also exhibit the same properties. This paper aims to derive and calculate the maximum frequency with which data can be transmitted on a long bus using two different approaches to calculate this limit in the presence of cross-talk and power noise. 1063-8210/$25.00 © 2008 IEEE