This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE JOURNAL OF SOLID-STATE CIRCUITS 1 A 265-μW Fractional-N Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS Hanli Liu , Member, IEEE, Zheng Sun, Student Member, IEEE, Hongye Huang , Student Member, IEEE, Wei Deng , Senior Member, IEEE , Teerachot Siriburanon , Member, IEEE, Jian Pang , Member, IEEE, Yun Wang , Rui Wu , Member, IEEE, Teruki Someya , Member, IEEE, Atsushi Shirane, Member, IEEE, and Kenichi Okada , Senior Member, IEEE Abstract— This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265-μW ultra-low- power operation. The proposed switching feedback can seam- lessly change the DPLL from sampling operation to sub-sampling operation without disturbing the phase-locked state of the DPLL to reduce the number of building blocks that works at the oscillator frequency, leading to significant power reduction. With the reduced number of high-frequency circuits, scaling the reference frequency is fully used to reduce the power consumption of the DPLL. Together with an out-of-dead-zone detector and a duty-cycled frequency-locked loop running in the background, the switching feedback achieves robust frequency and phase acquisition at start-up and helps the sub-sampling PLL recover when large phase and frequency disturbances occur. A transformer-based stacked- g m oscillator is proposed to minimize the power consumption while providing the sufficient swing to drive the subsequent stages. A truncated constant-slope digital-to-time converter is proposed to improve the power efficiency while retaining good linearity. The proposed fractional- N DPLL consumes only 265 μW while achieving an integrated jitter of 2.8 ps and a worst case fractional spur of -52 dBc, which corresponds to a figure of merit (FOM) of -237 dB. Index Terms— Constant slope, digital phase-locked loop (DPLL), digital-to-time converter (DTC), duty-cycled frequency- locked loop (DC-FLL), FLL, fractional- N, low power, out- of-dead zone (ODZ), PLL, sampling, sub-sampling, switching Manuscript received May 7, 2019; revised July 20, 2019; accepted August 14, 2019. This article was approved by Guest Editor Payam Heydari. This article is partially based on results obtained from a project commissioned by the New Energy and Industrial Technology Development Organization (NEDO). (Corresponding author: Hanli Liu.) H. Liu, Z. Sun, H. Huang, J. Pang, Y. Wang, T. Someya, A. Shirane, and K. Okada are with the Department of Electrical and Electronic Engi- neering, Tokyo Institute of Technology, Tokyo 152-8552, Japan (e-mail: liu@ssc.pe.titech.ac.jp). W. Deng is with the Department of Microelectronics and Nanoelectronics, Institute of Microelectronics, Tsinghua University, Beijing 100084, China. T. Siriburanon is with the School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, D04 V1W8 Ireland. R. Wu is with the Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China. Color versions of one or more of the figures in this article are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2019.2936967 feedback, transformer, truncated, ultra-low-power (ULP), ULP VCO, voltage-controlled oscillator. I. I NTRODUCTION T HE demand for ultra-low-power (ULP) circuits and sys- tems has exponentially increased with the growth of today’s system-on-chip (SoC) devices. SoC power reduc- tion greatly benefits battery-driven applications, such as the Internet-of-Things devices, sensor networks, and cellular net- works. Phase-locked loops (PLLs), one of the most important building blocks in the SoC devices, have recently drawn much research attention, as they account for a significant portion of device power consumption. For example, the PLL in [1] consumes nearly 48% of the total power of the receiver. The output of the fractional-N PLL has a much finer frequency resolution than that of an integer-N PLL and is thus used in a variety of applications. However, it consumes additional power to minimize the jitter-spur degradation caused by the fractional-N operation. Reducing the power consumption of a fractional-N PLL while maintaining good jitter and spur performance is very challenging. Digital PLLs (DPLLs) [2]–[16] are gaining more atten- tion over traditional analog PLLs due to their scalability in advanced CMOS technology and design portability across technologies. Another advantage of the DPLLs is their digital input–output that enables self-calibration, such as that of the bandwidth and the oscillator gain. Fig. 1 shows two low-power fractional-N DPLL architec- tures. They demonstrate a significant power reduction from the time-to-digital converter (TDC) because of the digital-to- time converter (DTC) [2]–[7]. Fig. 1(a) shows the so-called divider-based architecture [2]–[4]. It mimics the conven- tional charge-pump (CP) PLL operation by replacing the phase-frequency detector (PFD) and the CP with a TDC. Because the DTC reduces the quantization noise from the multi-modulus divider (MMD), a narrow-range TDC (NR- TDC) [2], [4] or even a bang-bang phase detector (BBPD) [3] can be used for the phase-quantizing operation to lower This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see http://creativecommons.org/licenses/by/4.0/