Network Time Synchronization: A Full Hardware Approach Jorge Juan, Julian Viejo, and Manuel J. Bellido Departamento de Tecnolog´ ıaElectr´onica, ETSI Inform´atica, Universidad de Sevilla, Spain jjchico@dte.us.es http://www.dte.us.es/id2 Abstract. Complex digital systems are typically built on top of sev- eral abstraction levels: digital, RTL, computer, operating system and software application. Each abstraction level greatly facilitates the design task at the cost of paying in performance and hardware resources usage. Network time synchronization is a good example of a complex system using several abstraction levels since the traditional solutions are a soft- ware application running on top of several software and hardware layers. In this contribution we study the case where a standards-compliant net- work time synchronization solution is fully implemented in hardware on a FPGA chip doing without any software layer. This solution makes it possible to implement very compact, inexpensive and accurate synchro- nization systems to be used either stand-alone or as embedded cores. Some general aspects of the design experience are commented together with some figures of merit. As a conclusion, full hardware implemen- tations of complex digital systems should be seen as a feasible design option, from which great performance advantages can be expected, pro- vided that we can find a suitable set of tools and control the design development costs. Keywords: digital systems, hardware, network time synchronization, FPGA. 1 Introduction Complex digital systems are typically built on top of several abstraction lev- els: digital, RTL, computer, operating system and software application. Each abstraction level, together with design automation tools, greatly facilitates the design task at the cost of the overhead introduced by every abstraction layer. This is payed in the form of reduced performance (both timing and power) and a much higher hardware resources usage. However, some critical parts in com- plex digital systems still require a low level implementation in order to improve performance or reduce power consumption. This is the case of the numerous hardware accelerators used today for audio and video processing that can be found in high performance or resource-limited devices like graphic adapters or