IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 4, APRIL 2006 977 Design and Anaylsis of A 2.5-Gbps Optical Receiver Analog Front-End in a 0.35- m Digital CMOS Technology Wei-Zen Chen, Member, IEEE and Chao-Hsin Lu Abstract—This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabri- cated in a low-cost 0.35- m digital CMOS process, this integrated circuit integrates both transimpedance ampliﬁer and post limiting ampliﬁer on a single chip. In order to facilitate high-speed opera- tions in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band ampliﬁer has been proposed. The measured input-referred noise of the optical receiver is about 0.8 A . The input sensitivity of the receiver front-end is 16 A for 2.5-Gbps operation with bit-error rate less than , and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is m m. Index Terms—Active inductor, limiting ampliﬁer (LA), tran- simpedance ampliﬁer (TIA). I. INTRODUCTION F IBER-OPTICAL networks have become a main stream for long haul and ultra high-speed data communications. The growing demands in broad-band access to internet, such as ﬁber to the home (FTTH), have motivated marvelous explorations of high performance optical transceivers recently [1]–[10]. This paper presents the design of a 2.5-Gbps optical receiver analog front-end (AFE) circuits in a low-cost 0.35- m digital CMOS process [1]. With the progress of CMOS photo detector (PD) technology, integrating photo detector, transimpedance ampli- ﬁer (TIA), and limiting ampliﬁer (LA) on a single chip provides the feasibility of system integration in the future [9]. The architecture of the optical receiver AFE is shown in Fig. 1. The incoming nonreturn to zero (NRZ) optical signal is converted to a photo current by an external photo detector, and regenerated to a voltage signal suitable for clock-and-data recovery (CDR) by a TIA and an LA. Conventionally, the TIA converts the tiny photo current generated from a photo detector to a voltage signal of tens to hundreds millivolts, and couples it to a LA in the other package for post ampliﬁcation. Since the Manuscript received December 20, 2004; revised April 28, 2005 and September 6, 2005. This work was supported by the National Science Foun- dation under Contract NSC-93-2220-E009-004, 93-EC-17-A-07-S1-001, by ITRI/STC, and by MediaTek Inc. This paper was recommended by Associate Editor K. Pedrotti. W.-Z. Chen is with the Department of Electronics Engineering and Innovative Package Research Center (IPRC), National Chiao-Tung University, Hsin-Chu 300, Taiwan, R.O.C. (e-mail: wzchen@mail.nctu.edu.tw). C.-H. Lu is now with Mediatek Inc., Hsin-Chu 300, Taiwan, R.O.C. Digital Object Identiﬁer 10.1109/TCSI.2005.862068 TIA’s output signal is still small, off-chip voltage coupling is susceptible to noise disturbance. In this design, both the TIA and the LA are integrated in a single chip. Thus, TIA’s output can be on chip dc-coupled to the LA, and no external coupling capacitor is required to min- imize noise interference. Furthermore, data jitter induced by low cutoff frequency in ac-coupled scheme can be alleviated. For on-chip dc-coupling, an automatic dc level control circuit (ADC) is incorporated as TIA’s output stage to adjust its output dc level to that of the post-LA’s input dc level. This paper is organized as follows. Section II describes the de- sign of the TIA in the receiver. Several bandwidth enhancement techniques for CMOS TIA’s have been utilized. Its noise perfor- mance is also analyzed and discussed. The design of LA is in- troduced in Section III. The LA is basically a cascaded ampliﬁer chain. The gain-bandwidth performance and power optimization are investigated in detail. Section IV describes the experimental results. And ﬁnally, conclusions are drawn in Section V. II. TRANSIMPEDANCE AMPLIFIER For CMOS TIAs, the primary factors that constrain signal bandwidth and noise performance are the inherent parasitic ca- pacitance introduced by the photo detector and the bonding pad. Therefore, in a conventional common source TIA architecture, its signal bandwidth has to be severely compromised with con- version gain and noise performance [2]. In this design, a low input impedance TIA using regulated cascode input stage [3] with shunt-feedback conﬁguration is utilized [4]. Fig. 2 depicts the circuit schematic of the TIA. The input impedance of the TIA is greatly reduced by the local feedback ampliﬁer and shunt-feedback. This prevents the input pole from dominating signal bandwidth, and the gain degradation caused by the input shunting capacitance can be avoided. To further enhance signal bandwidth, inductive loads at each gain stage are also utilized to partially trim out the parasitic ca- pacitance at the drain of and [4], [5]. Compared to using resistive loads, signal bandwidth is improved by 80% without gain peaking according to experimental results [4]. In this de- sign, active inductors are employed instead of passive spiral in- ductors for the latter ones are in general bulky and contribute signiﬁcant parasitic capacitance. The active inductors are made up of an nMOS and a resistor, and are conﬁgured as , , and . The nMOS is operated in the sat- uration region, and the resistor is implemented using a pMOS operated in the triode region. Let and be the parasitic 1057-7122/$20.00 © 2006 IEEE