Circuits Syst Signal Process DOI 10.1007/s00034-016-0369-5 Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines Davide De Caro 1 · Fabio Tessitore 1 · Gianfranco Vai 2 · Gerardo Castellano 1 · Ettore Napoli 1 · Nicola Petra 1 · Claudio Parrella 3 · Antonio G. M. Strollo 1 Received: 3 November 2015 / Revised: 11 July 2016 / Accepted: 13 July 2016 © Springer Science+Business Media New York 2016 Abstract NAND-based digitally controlled delay-lines (DCDLs) are employed in several applications owing to their excellent linearity, good resolution and easy stan- dard cell design. A glitch-free DCDL behavior is often a strict requirement [e.g. spread-spectrum clock generators (SSCG) and digitally controlled oscillators]. Exist- ing glitch-free NAND-based DCDL topologies either require two flip-flops for each DCDL delay-element (DE) or present a very long settling time which limits the maxi- B Davide De Caro dadecaro@unina.it Fabio Tessitore fabio.tessitore@unina.it Gianfranco Vai gianfranco.vai@st.com Gerardo Castellano gerardo.castellano@unina.it Ettore Napoli etnapoli@unina.it Nicola Petra nicpetra@unina.it Claudio Parrella claudio.parrella@st.com Antonio G. M. Strollo astrollo@unina.it 1 Department of Electrical Engineering and Information Technology, University of Napoli Federico II, via Claudio, 21, 80125 Naples, Italy 2 STMicroelectronics, Milan, Cornaredo, Italy 3 STMicroelectronics, Naples, Arzano, Italy