Energy-Efficient Multicore Chip Design Through Cross-Layer Approach Paul Wettin, Jacob Murray, Partha Pande, Behrooz Shirazi School of Electrical Engineering and Computer Science Washington State University Pullman, USA {pwettin, jmurray, pande, shirazi}@eecs.wsu.edu Amlan Ganguly Department of Computer Engineering Rochester Institute of Technology Rochester, USA amlan.ganguly@rit.edu Abstract—Traditional multi-core designs, based on the Network-on-Chip (NoC) paradigm, suffer from high latency and power dissipation as the system size scales up due to the inherent multi-hop nature of communication. Introducing long-range, low power, and high-bandwidth, single-hop links between far apart cores can significantly enhance the performance of NoC fabrics. In this paper, we propose design of a small-world network based NoC architecture with on-chip millimeter (mm)-wave wireless links. The millimeter wave small-world NoC (mSWNoC) is capable of improving the overall latency and energy dissipation characteristics compared to the conventional mesh-based counterpart. The mSWNoC helps in improving the energy dissipation, and hence the thermal profile, even further in presence of network-level dynamic voltage and frequency scaling (DVFS) without incurring any additional latency penalty. Keywords—NoC, wireless, mm-wave, small world, DVFS I. INTRODUCTION Continuing progress in integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multi-core chips widely adoptable in multiple domains. In the design of high-performance massively multi-core chips, power and heat are the dominant constraints. The increasing power consumption is of growing concern due to several reasons, e.g., cost, performance, reliability, scalability, and environmental impact. Increased power consumption can raise chip temperature, which in turn can decrease chip reliability and performance and increase cooling costs. Performance of a multicore chip is governed by its overall communication infrastructure, which is predominantly a NoC. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency, significant power consumption, and temperature hotspots arising out of long, multi-hop wireline links used in data exchange. It is possible to design high-performance, robust, and energy- efficient multi-core chips by adopting novel architectures inspired by complex network theory in conjunction with on- chip wireless links. Networks with the small-world property have a very short average path length, making them particularly interesting for efficient communication with minimal resources. Using the small-world approach [1], we can build a highly efficient NoC with both wired and wireless links. Neighboring cores should be connected through normal metal wires while widely separated cores will communicate through long-range, single-hop, wireless links. Wireless Network-on-Chip (WiNoC) is an enabling technology to integrate very high numbers of cores in a single chip [2]. By reducing the hop count between largely separated communicating cores, wireless shortcuts have been shown to carry a significant amount of the overall traffic within the network. The amount of traffic detoured in this way is substantial and the low power wireless links enable energy savings. The overall energy dissipation of the WiNoC can be improved even further if the characteristics of the wireline links are optimized according to the traffic patterns. Dynamic voltage and frequency scaling (DVFS) is a popular methodology to optimize the power usage/heat dissipation of electronic systems without significantly compromising overall system performance [3]. In this work our aim is to demonstrate how the power and thermal efficiencies of multi-core chips can be improved by adopting a cross-layer design methodology by deploying long-range wireless interconnects as well as incorporating suitable DVFS schemes on the wireline links. II. RELATED WORK Various research groups have investigated power and thermal management of multicore-based computing platforms. Dynamic voltage and frequency scaling (DVFS) is a popular methodology to optimize the power usage/heat dissipation of electronic systems without significantly compromising overall system performance DVFS can be applied to multi-core processors; to all cores or to individual cores independently [4]. Multi-core chips implemented with multiple Voltage Frequency Island (VFI) design styles are other promising alternatives. VFI is shown to be effective in reducing on-chip power dissipation [5][6]. Various research groups have addressed designs of appropriate DVFS control algorithms for VFI systems [7]. Some researchers have also recently discussed the practical aspects of implementing DVFS control on a chip, such as tradeoffs between on-chip versus off-chip DC-DC converters [4], the number of allowed discrete voltage levels, and centralized versus distributed control techniques [3]. Thermal-aware techniques are principally related to power- aware design methodologies using DVFS [8]. It is shown that distributed DVFS provides considerable performance improvement under thermal duress [8]. Most of the existing works principally addresses power and thermal management strategies for the processing cores only. Networks consume a significant part of the chip’s power budget; greatly affecting overall temperature. However, there is This work was supported in part by the US National Science Foundation (NSF) grants CCF-0845504, CNS-1059289, and CCF-1162202, and Army Research Office grant W911NF-12-1-0373. 978-3-9815370-0-0/DATE13/©2013 EDAA