1322 IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 10, OCTOBER 2011 Cryogenic Operation of Junctionless Nanowire Transistors Michelly de Souza, Member, IEEE, Marcelo A. Pavanello, Senior Member, IEEE, Renan D. Trevisoli, Rodrigo T. Doria, and Jean-Pierre Colinge, Fellow, IEEE Abstract—This letter presents the properties of nMOS junc- tionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maxi- mum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature. Index Terms—Junctionless transistor, low temperature, nano- wire transistor, silicon-on-insulator (SOI), threshold voltage model. I. I NTRODUCTION T HE JUNCTIONLESS nanowire transistor (JNT) has been recently proposed as a promising alternative to circumvent the problem of realizing ultrasharp doping concentration gradi- ents in junctions for advanced CMOS technologies [1]. Unlike from inversion-mode (IM) transistors, these devices present a heavy doping concentration, which is constant along the drain, channel, and source. JNTs have already been shown to provide advantages over IM multiple-gate devices, such as improved short-channel characteristics, namely, reduced threshold volt- age roll-off and DIBL [2]. The electrical characteristics of JNTs at high temperature have been recently reported in [3]. However, no information regarding the cryogenic temperature operation of JNTs is available in the literature yet. In this letter, an evaluation of the cryogenic operation of JNTs is presented. Measurements of drain current, subthresh- old slope, maximum transconductance, and threshold voltage Manuscript received May 31, 2011; revised July 2, 2011; accepted July 4, 2011. Date of publication August 17, 2011; date of current version September 28, 2011. This work was supported in part by the Brazilian research- funding agencies CAPES, FAPESP, and CNPq, by SFI under Grant 05/IN/I888, and by the EC FP7 through the NoEs NANOSIL and EUROSOI+ (Contracts 216171 and 216373). The review of this letter was arranged by Editor L. Selmi. M. de Souza and R. T. Doria are with the Centro Universitário da FEI, São Bernardo do Campo 09850-901, Brazil (e-mail: michelly@fei.edu.br; rtdoria@fei.edu.br). M. A. Pavanello is with the Centro Universitario da FEI, São Bernardo do Campo 09850-901, Brazil, and also with LSI/PSI/USP, São Paulo 05508-900, Brazil (e-mail: pavanello@fei.edu.br). R. D. Trevisoli is with LSI/PSI/USP, University of Sao Paulo, São Paulo 05508-900, Brazil (e-mail: renantd@lsi.usp.br). J.-P. Colinge is with the Tyndall National Institute, University College Cork, Cork, Ireland (e-mail: jean-pierre.colinge@tyndall.ie). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2011.2161748 (V TH ) are reported for fabricated devices measured at temper- atures down to 90 K. A threshold voltage model is proposed to explain its variation with temperature. II. DEVICE FABRICATION AND CHARACTERISTICS JNTs were fabricated on standard silicon-on-insulator (SOI) wafers, featuring 340-nm buried oxide, following the pro- cess described in [1]. The silicon layer was thinned down to 10–15 nm and patterned into nanowires using e-beam lithog- raphy. Using this technique, devices with as-written fin width (W fin ) ranging between 23 and 40 nm and fin height (H) of 10 nm were obtained. However, the effective nanowire width is expected to be reduced due to processing steps. Gate oxidation has been performed, and ion implantation has been carried out to produce nMOS JNTs with different doping concentrations, varying from 1 ×10 19 cm −3 to 5 ×10 19 cm −3 . The gate stack is formed by a 10-nm-thick gate oxide (t ox = 10 nm) and 50-nm-thick P+ polycrystalline silicon. IM trigate nMOSFET featuring the same dimensions, with channel doping concentra- tion N A = 10 18 cm −3 and source/drain doping concentration N A = 10 20 cm −3 , was also fabricated for comparison pur- poses. Although long-channel devices (L = 1 μm) were used in this study, the performed analysis and conclusions can be extended to short-channel JNTs [2]. III. RESULTS AND DISCUSSION Drain current (I DS ) as a function of the gate voltage (V GF ) curves at low drain bias (V DS = 50 mV) were experimentally obtained for several nMOS JNTs with variable W fin over a wide temperature (T ) range. Fig. 1 shows the measured I DS as a function of V GF (a) as well as the gate voltage overdrive, V GT = V GF − V TH (b), for a JNT with W fin = 30 nm and N D = 5 × 10 19 cm −3 , for T ranging from 90 K to 200 K. The T reduction causes two different effects that affect the current drive in MOS transistors: the increase of V TH , which tends to decrease I DS , and the carrier mobility raise, which tends to increase it. For a given bias point [zero-temperature coefficient (ZTC)], both effects compensate each other, and I DS does not depend on T . Above this point, mobility increase with T reduction is responsible for I DS increase. However, as can be seen in the results in Fig. 1(a), no ZTC point has been observed for JNTs, and I DS has shown to decrease with T reduction. The subthreshold slope (SS) is shown in Fig. 2 (left axis) for a JNT and an IM trigate nMOSFET, both with W fin = 30 nm. The results show that the SS is about 6 mV/dec higher than the theoretical limit over the entire T range for the JNT and IM transistors, which is in agreement with the data re- ported in [1] for higher temperatures where similar values were 0741-3106/$26.00 © 2011 IEEE