A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors Renan Doria Trevisoli a,⇑ , Rodrigo Trevisoli Doria b , Michelly de Souza b , Marcelo Antonio Pavanello a,b a LSI/PSI/USP, University of São Paulo, Av. Prof. Luciano Gualberto, trav. 3, n. 158, 05508-900 São Paulo, Brazil b Department of Electrical Engineering, Centro Universitário da FEI, Av. Humberto de Alencar Castelo Branco n. 3972, 09850-901 São Bernardo do Campo, Brazil article info Article history: Available online xxxx Keywords: Junctionless nanowire transistors Threshold voltage Analytical model Parameter extraction abstract This work proposes a physically-based definition for the threshold voltage, V TH , of junctionless nanowire transistors and a methodology to extract it. The V TH is defined as the point of equal magnitude for the drift and diffusion components of the drain current. The methodology for V TH extraction uses the device trans- conductance over drain current ratio characteristics. An analytical model for the threshold voltage based on the same definition has also been developed. Both V TH extraction method and model have been vali- dated through 3D simulations and have been applied to experimental devices. The proposed method has shown to provide a correct dependence on the temperature, while the double derivative of the drain cur- rent method overestimates this variation. Ó 2013 Elsevier Ltd. All rights reserved. 1. Introduction Multiple gate devices are known for providing better electro- static control of the charge in the channel region, therefore reduc- ing short-channel effects in comparison to planar transistors [1–6]. In general, all devices are based on the use of PN or Schottky junc- tions. For transistors of reduced channel length in the order of decananometers, extremely high doping density gradients are re- quired to form PN junctions, which requires the development of novel doping techniques and ultrafast annealing methods [7]. In order to overcome this drawback, Junctionless Nanowire Transis- tors (JNTs), also called gated resistor and pinch-off FET, have re- cently been proposed [7–11]. These devices present a constant doping profile from source to drain, such that no junctions and no doping gradients are required. JNTs are heavily doped (n-type for nMOS and p-type for pMOS) silicon nanowires surrounded by the gate stack. This device works similarly to an accumulation-mode SOI MOSFET (AMSOI) [12]. The silicon nanowire is fully depleted in subthreshold operation. The threshold voltage (V TH ) is reached when a portion of the channel is no longer depleted, such that bulk current flows through a neu- tral path. When the gate voltage (V G ) is raised above V TH in an nMOS JNT, the depth of the depletion decreases, increasing the neutral channel and the bulk current. When V G is equal to the flat- band voltage, the entire channel region is neutral and, for higher V G values, an accumulation layer forms near the interfaces. However, JNTs operate mostly in partial depletion with a reduced electric field in the neutral channel whereas AMSOI transistors work mainly in accumulation with a high electric field [7,13]. Also, the bulk current in JNTs is much larger than the one in AMSOI due to the heavier doping concentration and consequent increase in mo- bile carrier concentration [7]. Fig. 1 presents a schematic view of a triple-gate JNT (A), as well as its longitudinal section (B). The nanowire width and height, the gate oxide and buried oxide thick- ness and the channel length are noted W, H, t ox , t Box and L, respec- tively. Another feature of these devices is the high flexibility for achieving different threshold voltages that can be achieved by varying the nanowire cross section dimensions [7,13]. JNTs also present a higher V TH dependence on temperature than trigate inversion-mode devices [14–16]. Several recent studies have been focused on characterizing and modelling these devices [16–21]. The most commonly used meth- od to extract the threshold voltage in MOS transistors is the max- imum of the double derivative (DD) of the drain current [22]. However, this method fails at providing a physical meaning related to the device conduction. Therefore, in this work a current-based threshold condition is defined for JNTs (Section 2) and an extrac- tion method is proposed (Section 3). The method is validated in Section 4. An analytical equation for V TH is presented in Section 5 and the method is applied to experimental devices in Section 6. Fi- nally, Section 7 presents the conclusions. 2. Threshold voltage definition As already mentioned in Section 1, in JNTs the silicon nanowire is fully depleted in the subthreshold regime. Under this condition, there is a potential barrier in the channel region, such that when a 0038-1101/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2013.02.059 ⇑ Corresponding author. E-mail address: renantd@lsi.usp.br (R.D. Trevisoli). Solid-State Electronics xxx (2013) xxx–xxx Contents lists available at SciVerse ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse Please cite this article in press as: Trevisoli RD et al. A physically-based threshold voltage definition, extraction and analytical model for junctionless nano- wire transistors. Solid State Electron (2013), http://dx.doi.org/10.1016/j.sse.2013.02.059