Design and Implementation of a Multi-Terabit Optical Burst/Packet Router prototype F. Masetti, D. Zriny, D. Verchère, J. Blanton, T. Kim, J. Talley (1) D. Chiaroni, A. Jourdan, J.-C. Jacquinot, C. Coeurjolly, P. Poignant (2) M. Renaud (3) G. Eilenberger, S. Bunse, W. Latenschleager, J. Wolde, U. Bilgak (4) Alcatel Research & Innovation 1000 Coit Rd, Plano, Tx, 75075, USA (1); Route de Nozay, F-91460 Marcoussis, France (2); OPTO+ Route de Nozay, F-91460 Marcoussis, France (3); Holderaeckerstr. 35, 70499, Stuttgart, Germany (4) Contact: francesco.masetti-placci@alcatel.com Abstract: This paper reports the first demonstration of a multi-Terabit IP optical router. A sub-equipped rack-mounted prototype has been designed and assembled, demonstrating all key functions of large, scalable packet router. The design exploits burst switching techniques through to an integrated optical packet switching fab ric. Introduction Future routers for IP core networks will soon cross the Terabit capacity barrier, requiring vendors to investigate new architectures and technologies. In this paper, we report implementation of a rack-mounted prototype, assembled as a proof- of-concept for a scalable multi-Terabit IP optical router (TIPOR). The design is based on the new technique of burst switching coupled to an optical packet switching fabric. The technology building blocks, the design and techniques used to implement the optical packet switching matrix have been reported in [1][2]. This paper reports the final implementation and analysis of all functionalities, including burst assembly, switch control and scheduling, framers/transceivers and optical switching matrix. The viability of the approach is assessed showing experimental and simulation results. Concept description Current approaches to implement terabit routers consist of using parallel, multi-stage architectures switching small internal cells. We have investigated the feasibility of another approach based on a single- stage optical switching fabric and a larger switched granularity called a burst, which consists of aggregation of IP packets (or ATM cells). This concept has advantages: - relaxed requirements for processing speed: aggregation into bursts allows increase of data rate and scalability of the fabric and router capacity with limited impact on control; - relaxed switch arbitration and contention management: it is expected that a single-stage Time-Space-Time switch should be simpler to handle. Adapted algorithms have been developed to study scalability and complexity of the process. In particular, the latency can be reduced due to limited buffers in cascade. - expected higher robustness due to simpler of the fabric structure, limited number of components, simpler monitoring. To implement a single stage core switch, we adopted an optical switching matrix, as opposed to electronics, for these reasons: - relaxed interconnection problems, as bit-rate increases, due to the advantage of optics in this respect. In fact, an optical switching matrix represents the natural extension of passive optical interconnects widely used; - wire- speed switching of packets without parallel demultiplexing, as with electronics, scalable to future higher bit rates; - availability and acceptable maturity of some optical technologies (optical gates, tunable lasers, ...) to consider their integration and exploitation in a packet switching system. Fast Optical Switching Matrix IP packets/ ATM Cells 1 read per “Slot Cell” time (1 μs) Rate of writes/reads determined by switch fabric speed-up Output Scheduling Output Scheduling Output Scheduling Ingress Burst Card Burst Switching (Bufferless) L1 Input Scheduling 1 write per “Slot Cell” time (1μs) Aggregation Optical Packets Egress Burst Card De-aggregation X C V X C V X C V X C V X C V X C V L1 Input Scheduling L1 Input Scheduling L2 Scheduling Switch Arbitration Requests / Grants BC 1 BC16 BC i BC 1 BC i BC16 VOQ VOQ VOQ OQ OQ OQ Configuration Fig. 1: TIPOR prototype architecture (left) and rack-mounted assembly (right) Prototype implementation The four main functions required to design our router are: (1) the aggregation of packets into bursts and contention resolution (burst card (BC)), (2) the scheduling for a single-stage multi-terabit switch, (3) the physical interface to the switching matrix (transceivers (XCV)) and (4) the optical fast switching matrix itself. These four functions have been implemented in a rack-mounted prototype, which includes BCs with 10 Gbit/s throughput (designed scalable up to 160 Gbit/s), burst framer/transceiver boards with 10 Gbit/s throughput, and an optical fast packet switching matrix designed for 640 Gbit/s (scalable to 2.56 Tbit/s), to demonstrate all functionalities. The adopted burst size is 9 kbit/s, easy to implement, but also a reasonable trade -off between routing constraints and aggregation efficiency. The