644 IEICE TRANS. ELECTRON., VOL.E96–C, NO.5 MAY 2013 PAPER Special Section on Fundamentals and Applications of Advanced Semiconductor Devices Rigorous Design and Analysis of Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric and Tunneling-Boost n-Layer Jae Hwa SEO † , Jae Sung LEE † , Yun Soo PARK † , Jung-Hee LEE †† , Nonmembers, and In Man KANG †† a) , Member SUMMARY A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Ap- plication of local high-k gate-dielectric and n-layer leads to reduce the tun- neling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (I on ) characteristics of TFETs. For optimal de- sign of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (L high-k ) for the fixed n- layer length (L n-layer ). The simulation results have been analyzed in terms of on- and off- current (I on and I off ), subthreshold swing (SS), and RF per- formances. key words: gate-all-around (GAA), tunneling field-effect transistor (TFET), tunneling-boost n-layer, hetero-gate dielectric 1. Introduction The modern CMOS technology based on silicon has been developed with the continuous down-scaling. However, the scaling of CMOS technology is faced with a lot of tech- nological problems. The tunneling field-effect transistor (TFET) is one among the most promising solutions for the scaling limit. TFETs are the efficient low-standby power (LSTP) devices which have advantages such as low sub- threshold swing (SS) and immunity for short-channel ef- fects (SCEs) [1]–[5]. However, the low on-current (I on ) level is the critical problem of the planar silicon-based TFETs. In order to solve this problem, TFETs with various struc- tures (double-gate, gate-all-around, and so on.) and materi- als (high-k, Ge, GaAs, and so on.) have been studied [6]– [17]. In this situation, we have focused on the way of re- ducing the tunneling barrier width in order to increase the on-current. To reduce the tunneling barrier width, we try to combine the n-layer and high-k dielectric region. Recently, we studied about Ge and GaAs heterojunction tunneling de- vice with n-layer region [18]. But it is very complicate to apply normal CMOS fabrication system. Thus in this paper, we studied the silicon-based GAA TFET with n-layer and high-k dielectric region that can be used in the low power silicon CMOS application. Based on a proceeding research Manuscript received August 25, 2012. Manuscript revised November 20, 2012. † The authors are with School of Electrical Engineering and Computer Science, Kyungpook National University, 1370, Sankyuk-dong, Buk-gu, Daegu, 702-701, Korea. †† The authors are with School of Electronics Engineering, Kyungpook National University, 1370, Sankyuk-dong, Buk-gu, Daegu, 702-701, Korea. a) E-mail: imkang@ee.knu.ac.kr DOI: 10.1587/transele.E96.C.644 for GAA TFET with n-layer (GAA PNPN TFET) [19], we select the local high-k dielectric length (L high-k ) as the op- timization parameter. The DC and RF parameters such as on-current (I on ), off-current (I off ), SS, cut-off frequency ( f T ), and maximum oscillation frequency ( f max ) are extracted and investigated with the optimization process. 2. Device Structure and Simulation Figure 1 is the structure of GAA PNPN TFET with local high-k gate dielectric (GAA HG PNPN TFET) with 60 nm gate length (L G ) which was simulated by using the ATLAS 2D TCAD simulator with the nonlocal band-to-band tun- neling (BTBT) model in the cylindrical coordinates [20]. This device is based on silicon. And the nonlocal BTBT model describe the tunneling mechanisms which occur be- tween valence band and conduction band that existed be- tween p+ source region and intrinsic body region. Also, nonlocal BTBT model consider the spatial variation of the energy band in order to model the tunneling process more accurately. The adopted local high-k material is hafnium oxide (HfO 2 ) and tunneling-boost n-layer doping concentra- tion (D n-layer ) is arsenic 1 × 10 19 cm -3 . The souce and drain doping concentrations (D s and D d ) are boron 1 × 10 20 cm -3 and arsenic 1 × 10 20 cm -3 respectively. The channel radius (R) and gate oxide thickness (t ox ) are 10 nm and 2 nm, in sequence. The hetero dielectric material which combination of HfO 2 and SiO 2 increase fabrication complexity. But by hybrid configuration of gate insulator, the ambipolar behav- ior is suppressed compare to high-k only TFET [6]. And Fig. 1 Cross-sectional view for 3D structure of GAA HG PNPN TFET with 60 nm channel length and 8 nm n-layer length. Copyright c  2013 The Institute of Electronics, Information and Communication Engineers