20 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART B, VOL. 21, NO. 1, FEBRUARY 1998 A High Performance MCM-D/C Application Eric D. Perfecto, Member, IEEE, Hai P. Longworth, Raed A. Sherif, Michael J. Ellsworth, and Roy Yu, Jr. Abstract—Mid-range computer performance is fast approach- ing speeds once considered appropriate for only high-end systems. IBM mid-range computer performance enhancement is enabled by the PowerPC RISC technology and the ability to effectively package the chips to maximize their electrical performance. MCM-D/C, coupled with IBM’s controlled collapsed chip con- nection (C4) offers an optimized solution for high performance modules. This paper describes a state-of-the-art seven chip MCM-D/C package currently under production for use as a processor mod- ule for the high end of IBM’s AS/400 Advanced Series with PowerPC. The package consist of a 63.0 mm metallized ceramic PGA substrate with 5 levels of Cu-Polyimide nonplanar thin films. It provides the interconnection for 7 high-performance Bi-CMOS logic and memory chips. Each chip has over 2600 C4 connections divided between power, signal and ground. The terminal metal layer provides the C4 pads for chip connection, as well as special repair wiring available for the repair of defects created during the fabrication process. Up to 220 watts are dissipated with air cooling while maintaining high module reliability. Index Terms—Cooling, flip chip, MCM-D/C, MCM implemen- tation, polyimide/Cu thin films, reliability. I. INTRODUCTION T HE relentless push for performance by increasing the level of integration and speed of silicon ASICS and microprocessors has also pushed packaging requirements. This is especially true for wiring density, rise time, and power density. In turn, thin film complexity has increased since the concept of lossy thin film MCM’s was first suggested by Ho in 1980 [1]. IBM is utilizing a high performance MCM-D/C package in their PowerPC AS microprocessor for the high end of the AS/400 Advanced Series with PowerPC technology [2], [3]. The module achieves 153 MHz clock speed during chip to chip communication. This paper will describe the thin film technology used to manufacture MCM-D/C substrates which provide the intercon- nection and power distribution for seven high-performance Bi- CMOS chips (a processor unit, a floating point processor unit, four storage control units, and an off-module control/interface unit). In addition to the details of the thin film process technology used in the fabrication of this substrate, there will be discussion of the C4 interconnection, as well as the module thermal solution and reliability. Manuscript received July 24, 1997; revised November 18, 1997. E. D. Perfecto, H. P. Longworth, R. A. Sherif, and R. Yu, Jr. are with IBM Microelectronics, Hopewell Junction, NY 12533 USA (e-mail: perfecto@us.ibm.com). M. J. Ellsworth is with IBM Corporation, Poughkeepsie, NY 12601 USA. Publisher Item Identifier S 1070-9894(98)01482-0. Fig. 1. High performance module. TABLE I MODULE AND INTERCONNECTION DESCRIPTION II. MCM-D/C MODULE Fig. 1 shows a picture of the module with seven flip chips and 94 decoupling capacitors. Table I provides a description of the module including the interconnection, cooling and encapsulation parameters. A. MCM-D/C Substrate Package wiring and power distribution is handled with 30 layers of 9211 alumina ceramic and five layers of thin film metal. Module wiring is distributed 81% in the thin film and 19% in the substrate. The alumina substrate has eight plane 1070–9894/98$10.00  1998 IEEE