ORIGINAL PAPER Impact of Mole Fractions due to Work Function Variability (WFV) of Metal Gate on Electrical Parameters in Strained SOI-FinFET Rajesh Saha 1 & Brinda Bhowmick 2 & Srimanta Baishya 2 Received: 11 February 2019 /Accepted: 15 April 2019 # Springer Nature B.V. 2019 Abstract In the recent sub-20 nm technology node, the process variability issues have become a major problem for scaling of MOS devices. We present a design for a strained Si/SiGe FinFET on an insulator using a 3D TCAD simulator. The impact of metal gate work function variability (WFV) on electrical parameters is studied. Such impact of WFV for different mole fractions (x) of the SiGe layer in a strained SOI-FinFET with varying grain size is presented. The results show that as the mole fraction is increased, the variability in threshold voltage (σV T ) and off current (σI off ) is decreased; while, the variability of on-current (σI on ) is increased. A notable observation is the distribution of electrical parameters approaches a normal distribution for smaller grain sizes. Keywords Grain orientation . Metal gate granularity . Mole fraction . Strained SOI-FinFET . Work function variability 1 Introduction It is well known that the benefits of MOSFET scaling are always accompanied by adverse effects, commonly known as short channel effects (SCEs), on their performance as well [1]. To control the adverse effects, there has been a constant hunt for alternatives to MOS structures. The FinFET is one such devices, which is already in production with its better capability to control SCEs [2]. Along with the novel device structures, various engineering technologies like gate work function engineering [3, 4], modification of structure [5, 6], strain engineering [7], gate oxide engineering [8] etc., can be useful for future low-power applications. Strain engineering is used to enhance the carrier mobility in the channel. Tensile stress across the channel can be generated using strained sili- con on insulator (SSOI) to increase the driving current [9, 10]. An asymmetrically doped stacked channel SSOI FinFET has a lower value of off current than a lightly doped one due to change in bandgap [11]. The band structure of n-type SiGe FinFET on a relaxed SiGe substrate with varying Ge content shows that the pure Si channel is better in terms of drive current [12]. In the nanometer regime, process variability is one of the major issues. The various causes of the process of variability are random dopant fluctuation (RDF) [13], line edge rough- ness [14], and work function variability [15]. These variations have a strong influence on the electrical characteristics of the device. In advanced CMOS technology, metal is used as gate material instead of polysilicon to eliminate gate polysilicon depletion effect which leads to enhancement in threshold volt- age controllability [16]. But, a metal gate has different work functions in different orientations, which creates a random variation in threshold voltage within the gate area [17–19]. This effect depends on various parameters like grain shape [20] and also the fin shape in the FinFETs [21]. Triangular fins have larger variation in threshold voltage than rectangular fins in presence of TiN metal gate of strained SOI FinFET [22]. In our recent work, a new device architecture named step-FinFET was proposed and a comparative study of elec- trical parameters between step-FinFET and conventional FinFET was presented in presence of WFV of Ti metal gate [19]. In this paper, a simulation study of a strained Si/SiGe FinFET which is similar to the strained Si-MOSFET on SiGe on insulator substrate [9] is reported. This work presents * Rajesh Saha rajeshsaha93@gmail.com 1 School of Electronics Engineering, Vellore Institute of Technology Andhra Pradesh, Amravati AP-522237, India 2 Electronics and Communication Engineering Department, National Institute of Technology Silchar, Assam 788010, India Silicon https://doi.org/10.1007/s12633-019-00163-z