International Journal of Scientific Engineering and Technology (ISSN : 2277-1581) www.ijset.com, Volume No.1, Issue No.2 pg:59-64 01 April 2012 59 Superiority of Current mode over Voltage mode Interconnects Yash Agrawal,Rohit Dhiman, Rajeevan Chandel # Department of Electronics & Communication Engineering National Institute of Technology, Hamirpur 177 005, Himachal Pradesh, India mr.yashagrawal@gmail.com, rohitdhiman.nitham@gmail.com, rajevanchandel@gmail.com Abstract- In deep submicron VLSI circuits, interconnect delays dominate MOSFET gate delays. Conventional buffer insertion method reduces delays at the cost of valuable chip area. Consequently, alternative methods are essential. Current mode interconnects have lesser delay than voltage mode circuits and also consume lesser chip area. In the present work, superiority of current mode over voltage mode interconnects is analyzed. The simulative analysis is carried out using Tanner EDA tools. I. INTRODUCTION Interconnects are supposed to be skeleton of VLSI circuits but today it is acting as a major bottleneck. With technology scaling, device dimensions are decreasing. This is reducing device delay. However advancements in VLSI technology lead to increase in chip size. Scaled technologies and larger chip size facilitates huge chip functionality. This increases interconnect lengths, which in turn increases signal propagation delays. Thus at DSM technologies, the interconnect delays are becoming dominant than gate delays. Also, signal at the output are getting more distorted and noisy. Cross-talk effects are getting introduced due to increasing resistive and capacitive parasitics (R and C) of the interconnects. Interconnect design is thereby becoming major challenge for the VLSI design engineers. Hence alternative design methods are required to optimize and have better performance of the systems. Buffer insertion is an important method proposed by researchers to reduce long interconnects delays [1-4]. In buffer insertion, buffers are introduced in between the interconnects modeled as RC load. This reduces overall delay but at the same time, it requires high chip area and also increases power dissipation in the circuit [5-7]. Current mode interconnects are reported by various researchers to reduce interconnect delays [8-11]. In current mode interconnects, information is conveyed using current signal rather than voltage signal. It has very low output impedance. The current mode interconnects have higher performance as compared to voltage mode circuits. The current mode interconnects have less delay, less effect of supply voltage reduction and voltage swing reduction. It has higher bandwidth and less vulnerable to electrostatics discharge (ESD) [12]. The voltage and current mode interconnects are analyzed using SPICE simulations in the present work. The paper is arranged as follows. Section I introduces the topic. Section II deals with voltage mode interconnects. Section III describes the current mode interconnects. In section IV, superiority of the current mode interconnects over voltage mode interconnects is established. Section V presents results and discussions. Finally, conclusions are drawn in section VI. II. VOLTAGE MODE INTERCONNECTS Voltage mode signaling is most widely used in VLSI chips. In voltage mode signaling, receiver provides high input impedance (ideally infinity). The information is conveyed in the form of voltage. The output voltage is a function of input signal and is varied according to supply voltage. Fig.1 shows the theoretical model of conventional voltage mode interconnect implementation [10]. The output is terminated by an open circuit. Fig. 1. Voltage mode signaling. CMOS representation of voltage mode is shown in Fig. 2 [1,3]. The driver consists of an inverter which drives long RC interconnect chain. This is terminated by high input impedance of the inverter circuit at the receiver. This high input impedance of the receiver gives rise to high input capacitance which leads to high charging and discharging time for RC interconnect chain. Hence voltage mode signaling has large delay. Due to high input impedance at the receiver, the charge accumulated at the input of the receiver does not get effective V in R C R out =∞