I DDQ -based diagnosis at very low voltage (VLV) for bridging defects D. Arumi, R. Rodrı ´guez-Montan ˜ e ´s, J. Figueras, S. Eichenberger, C. Hora, B. Kruseman and M. Lousberg Bridging defects generate two currents related to the fault-free case: bridge current and downstream current. The latter may complicate the diagnosis of bridging defects. However, in CMOS technologies, the downstream current can be minimised at low power supply (V DD ) values, thus facilitating the diagnosis of such defects. Experimental evidence of this behaviour is presented. Introduction: I DDQ signatures [1] are a powerful method not only for testing but also for diagnosis purposes. They supply additional information that voltage tests are not able to provide. In particular, bridging defects cause typical I DDQ signatures with different current steps [2]. The number of current steps gives information about the transistor networks related to bridged nodes. The total defect current is composed of two components [3] (see Fig. 1): bridge current (I br ) and downstream current (I d ). Bridge current is the additional current caused by the non-desired short circuit between the p-MOS and n-MOS transistor networks affected by the defect. However, a brid- ging defect causes voltage degradation on the shorted nodes (V a and V b in Fig. 1). This voltage degradation may cause the gates driven by these nodes to consume more current than expected. The current on these gates is the so-called downstream current. The contribution of downstream current to the I DDQ signature results in the appearance of more current steps than initially expected, leading to erroneous diagnosis interpretations. This Letter shows the dependence of bridge and downstream current on V DD . The downstream current is minimised at low V DD values. V in 1 V in 2 V in 3 2 V in 4 V b a b V b l br l br V a V a l d l d R R nand 1 nand 2 inv inv 2 inv 1 inv 3 Fig. 1 Circuit examples with bridging defect a Between outputs of inverter and two-input nand gate b Between outputs of two inverters V b V a I br I d R b V in 4 V in 1 (0) V in 2 (0) V in 3 (1) Fig. 2 Defect current from example in Fig. 1a when V IN1 ¼ V IN2 ¼ 0 and V IN3 ¼ 1 Bridge against downstream current: Without loss of generality, let us consider Fig. 1a. The output of a two-input nand gate (nand1) and the output of an inverter (inv) are connected by a bridging defect with resistance R b . In the case of V a having a high value and V b having a low logic value, there is a current path flowing from the parallel p-network of nand1 to the n-network of inv (Fig. 2). Depending on the number of p-MOS transistors (nand1) in the on-state, different bridge current values are obtained. Assuming identical p-MOS transistors, two different paths can be activated depending on whether one or both transistors are in the on-state. The Hspice simulation results of the quiescent current consumption against power supply (V DD ) are shown in Fig. 3. At nominal V DD , points A and B refer to the consumption when two or only one p-MOS transistor is in the on-state, respectively. In this case, the I DDQ signature for this network configuration should lead to a two current level signature. 125 175 225 275 325 375 425 475 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 V DD , V I DDQ , μA A C D B V in 1 = V in 2 = V in 4 = 0 V in 3 = 1 V in 1 = V in 2 = 0 V in 3 = V in 4 = 1 V in 1 = V in 4 = 0 V in 2 = V in 3 = 1 V in 1 = 0 V in 2 = V in 3 = V in 4 = 1 Fig. 3 Current simulation results for different V DD values However, downstream current also contributes to the total current. The voltage degradation of V b makes the next nand gate (nand2) have higher consumption than expected (I d in Fig. 1a). This contribution depends on the other input value of nand2(V in4 ). If V in4 ¼ 0, the bridge current is the only contribution to the total current. However, when V in4 ¼ 1, there is a current path in nand2, as shown in Fig. 2. When V in4 ¼ 1, the total current (I br þ I d ), is denoted by points C and D in Fig. 3 for the cases when both or only one p-MOS transistor of nand1 is in the on-state, respectively. The current signature of this network configuration is now composed of four current levels owing to the downstream current contribution. In general, if the degraded nodes have a large fan-out, the number of current levels in the current signature may be high. Note that, for the case when (V a V b ) ¼ (0 1), only one current level should be reported, but because of the downstream current, two current levels are obtained. Defect current V DD dependence: It is known that the relationship between I DDQ and V DD gives information in order to distinguish fault- free from faulty devices [4]. In fact, for bridging defects, the two current components discussed in the previous Section behave differ- ently when V DD is modified. The difference lies in that bridge current comes from transistors in the ohmic state, whereas downstream current comes from transistors presumably in the saturated state. Without loss of generality, let us consider the example in Fig. 1b, where the outputs of two inverters (inv1 and inv2, one of which is driving another inverter (inv3), are bridged together. The downstream current is determined by the current of the transistors of inv3, which are in the saturated state. Considering the alpha-power model for MOS transistors, this current is I DSðSAT Þ ¼ k 2 V GS  V TH V DD  V TH   a ¼ k 2 V DD =2  V TH V DD  V TH   a ð1Þ where V TH is the transistor threshold voltage, a is a velocity saturation factor, and k is the process parameter. Notice that for low V DD values (V DD close to twice V TH ), the saturated current tends to zero. However, the bridge current depends on the current of the transistors belonging to inv1 and inv2. The current expression for these transistors in the ohmic state is I DSðOHMICÞ ¼ k 2 ðV GS  V TH Þ a=2 V DS ¼ k 4 V DD ðV DD  V TH Þ a=2 ð2Þ As can be observed in (2), although the current decreases for low V DD values, it does not tend to zero, even when V DD is close to 2V TH . This different behaviour for bridge and downstream current is seen in Fig. 3 for the example shown in Fig. 1a. The lines comprising points A and B correspond to the bridge currents for the two possible activated p-networks of nand1. However, the lines comprising points C and D depict the total current (I br þ I d ) for the two possible combinations of the p-network of nand1. For low V DD values, the value of the total Techset CompositionLtd, Salisbury Doc: D:/IEE/EL/43-5/52344.3d Digital electronics ELECTRONICS LETTERS 1st March 2007 Vol. 43 No. 5