  Citation: Spataro, S.; Spina, N.; Ragonese, E. Package-Scale Galvanic Isolators Based on Radio Frequency Coupling: Micro–Antenna Design. Electronics 2022, 11, 291. https:// doi.org/10.3390/electronics11030291 Academic Editor: J.-C. Chiao Received: 8 December 2021 Accepted: 15 January 2022 Published: 18 January 2022 Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affil- iations. Copyright: © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). electronics Article Package-Scale Galvanic Isolators Based on Radio Frequency Coupling: Micro–Antenna Design Simone Spataro 1 , Nunzio Spina 2 and Egidio Ragonese 1, * 1 Dipartimento di Ingegneria Elettrica Elettronica e Informatica (DIEEI), University of Catania, 95125 Catania, Italy; simone.spataro@phd.unict.it 2 STMicroelectronics, 95121 Catania, Italy; nunzio.spina@st.com * Correspondence: egidio.ragonese@unict.it; Tel.: +39-095-738-2331 Abstract: This paper presents the design of on-chip micro-antennas for package-scale galvanic isolators based on RF planar coupling. A step-by-step design procedure is proposed, which aims at the maximization of the weak electromagnetic coupling between the RX and TX antennas integrated on side-by-side co-packaged chips to enable both high isolation rating and common-mode transient immunity thanks to the high dielectric strength and low capacitive parasitics of a molding compound- based galvanic barrier, respectively. Micro-antenna design guidelines are drawn, highlighting the main relationship between coil coupling performance and their layout parameters, which are often in contrast with respect to traditional integrated inductor ones. Keywords: common-mode transient immunity (CMTI); electromagnetic coupling; galvanic isolation rating; on-chip antennas; package; radio frequency; tapered spiral 1. Introduction Nowadays, the adoption of isolation techniques is mandatory in order to improve safety and reliability in several applications (e.g., industrial sensors, medical equipment, gate drivers for motor control, etc.). A general block diagram of a galvanically isolated system is shown in Figure 1. Typically, two domains, A and B, must be galvanically isolated for two reasons i.e., one of them is subject to hazardous voltages, and/or different ground references are required. Data signals are transferred across the galvanic isolation barrier to enable bidirectional communication between the two interfaces. Figure 1. Simplified block diagram of a galvanically isolated system. According to the current standardization for semiconductor galvanic isolators [1], one of the most important performance parameters is the maximum surge isolation volt- age, V SURGE . It quantifies the capability of the isolator to withstand very high voltage impulses of a certain transient profile, which can arise from direct or indirect lightning Electronics 2022, 11, 291. https://doi.org/10.3390/electronics11030291 https://www.mdpi.com/journal/electronics