An ultra-low-power neural signal acquisition analog front-end IC Luat Tran, Hyouk-Kyu Cha * Department of Electrical and Information Engineering, Seoul National University of Science and Technology, 232 Gongneung-ro, Nowon-gu, PO: 01811, Seoul, Republic of Korea ARTICLE INFO Keywords: Analog front-end Neural recording amplifier Programmable gain amplifier Low-noise Inverter-stacking ABSTRACT A four-channel, power-efficient, low-noise neural recording analog front-end (AFE) integrated circuit (IC) comprised of a low-noise amplifier (LNA), a programmable gain amplifier (PGA), and buffers is presented. The proposed AC-coupled capacitive-feedback LNA utilizes the inverter-stacking technique for the core operational transconductance amplifier which achieves four-time reduction in noise at minimal power consumption. The proposed PGA provides additional gain with tunable filtering function where the high-pass cut-off and low-pass cut-off frequencies can be controlled to acquire action potential and local field potential signals either simulta- neously or separately. The overall AFE IC has a programmable gain range from 45 dB to 63 dB and achieves integrated input-referred noise of 3.16 μV RMS within the 10 kHz bandwidth, leading to a noise efficiency factor of 2.04 and power efficiency factor of 4.16. The AFE IC is implemented using 180 nm CMOS process and consumes 2.82 μW per channel powered from the 1-V supply voltage. 1. Introduction In recent years, thanks to the advancements of neuroscience, implantable neural signal recording systems are being used to monitor brain activities in the hopes of diagnosing and treating neurological disorders such as Parkinson’s disease, paralysis, and epilepsy [1,2]. In these bio-signal acquisition systems, the most important portion is the neural recording analog front-end (AFE) which directly interfaces with the electrode to acquire signal information and maintain its signal integrity during processing. The signals of interest are known as action potentials (AP, spikes) and local field potentials (LFP) which are both weak in amplitude (from a few hundred μV to several mV) and low in frequency (from 1 Hz to 7 kHz). Both APs and LFPs are needed to be recorded simultaneously or sometimes separately in order to provide a better understanding of organization of the synaptic inputs to neurons and the relationship between spikes and LFPs [3]. One of the important parameters in the AFE is the integrated input- referred noise performance which must be kept lower than the extra- cellular neural background noise which is around 5 to 10 μVrms. The neural recording amplifier, which is the first block in the AFE chain, is the dominant part in deciding the overall noise performance and thus must be designed carefully considering its noise-power tradeoff. Other design considerations in the AFE include; multi-electrode array interfacing capability [4,5] so that multiple number of neuron signals can be acquired simultaneously for better understanding of the brain functions, and programmable gain and filtering functions to support both AP and LFPs with various signal amplitudes. Considering wireless power transfer from an external device to power the overall system, the AFE should dissipate minimal power as the excessive heat created in the implant device may induce damage to the surrounding nerve tissues [6]. In addition, the die area should also be considered for multi-channel inte- gration with minimal number of external components to reduce the overall form factor of the system. As the first block of the AFE chain which decides much of the overall AFE performance, effort must be placed on the design of the neural amplifier. Specifically, the topology for the core operational trans- conductance amplifier (OTA) must be chosen correctly and carefully designed. Recently, current reuse techniques have been widely utilized for the core operational transconductance amplifier (OTA) design with the purpose of optimizing the power-noise trade-off for the neural amplifier [7–10]. In this paper, a power-efficient and low-noise neural recording AFE IC is proposed and its detailed design is presented. An improved inverter- stacked OTA is proposed with enhanced common-mode stability while the bias circuit utilizes the proposed complementary switch to reduce the settling time when power turns on. Each of the comprising blocks in the AFE is designed carefully to consume low-power while achieving target performances. Section 2 presents the overall architecture of the * Corresponding author. E-mail addresses: trancongluat95@gmail.com (L. Tran), hkcha@seoultech.ac.kr (H.-K. Cha). Contents lists available at ScienceDirect Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo https://doi.org/10.1016/j.mejo.2020.104950 Received 21 September 2020; Received in revised form 19 November 2020; Accepted 24 November 2020 Available online 30 November 2020 0026-2692/© 2020 Elsevier Ltd. All rights reserved. Microelectronics Journal 107 (2021) 104950