Enabling 3D Integration Through Optimal Topography Dae Hyun Kim 1 , Yen-Kuan Wu 2 , Rasit Onur Topaloglu 3 , and Sung Kyu Lim 1 1 Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, 30332 2 Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, 92093 3 GLOBALFOUNDRIES Email: daehyun@gatech.edu, yew002@ucsd.edu, rasit.topaloglu@globalfoundries.com, limsk@ece.gatech.edu Abstract— In a 3D stacked IC, through-silicon vias (TSVs) are utilized to interconnect dies vertically. In one common TSV practice, via-ﬁrst TSVs directly connect the ﬁrst metal layer of a die and the top metal layer of the die above it. However, the landing pads on the ﬁrst metal layer, due to their large area and presence of features with widely varying sizes, may result in serious topographic errors after chemical-mechanical polishing. These errors result in cumulative effects in up interconnect layer processing steps, thereby causing yield and performance problems. In this paper, we analyze the impact of TSV landing pads on topography and present a technique to minimize it. We ﬁrst show that traditional ﬁll methodology is inefﬁcient due to large metal density variations. After selecting best ﬁll possible through conducting design of experiments (DOEs), we run CMP simulations on another DOE to ﬁnd the impact of TSV to TSV pitch on ﬁnal topography. Finding a minimum pitch from this experiment, we apply force-directed TSV separation during placement. We achieve 24% ∼ 36% improvement in topography variation with only 0.5% ∼ 2.0% wirelength increase. The improvements presented herein will enable manufacturability of 3D circuits with reduced topographic variations. I. I NTRODUCTION Recently, three-dimensional integrated circuits (3D ICs) have emerged as a promising candidate to improve die-to-die latency of 2D (traditional) ICs. In a 3D IC, the dies are stacked vertically and connected with through-silicon vias (TSVs) as shown in Figure 1. Therefore, for the same logic design, the footprint area of a 3D IC implementation is smaller than a 2D IC. Several recent works ( [1] and [2]) have shown that smaller footprint area of a 3D IC leads to shorter total wirelength, which in turn leads to better chip performance [3]. 3D IC is enabled by the fabrication of TSVs and die-to-die bonding. In a via-ﬁrst TSV process, TSVs are etched through the silicon and ﬁlled with copper or tungsten. The topmost interconnect layer of one die is connected to the lowest interconnect layer (M1) of another die. TSV landing pads are used in M1 and M top layers to make the connection. TSV landing pads are laid out in the standard routing metal layer, hence a direct connection to the metal wires and eventually to transistors is possible. TSV landing pads are designed to be larger than TSVs to prevent overlay error [4]. In practice, a TSV landing pad can be many times wider than the minimum M1 feature size. For example, a typical TSV diameter in demonstration is about 3 to 5μm, whereas the minimum M1 wire width is 65nm in 45nm technology. Such a wide range of metal features increases the feature density mismatch signiﬁcantly, thereby resulting in topographic non-uniformities and large density gradients due to chemical-mechanical polishing (CMP) which is highly dependent on the underlying metal feature density [5], [6]. Fill synthesis has been widely used as a post-route process to achieve the uniform feature density and also to meet the target feature This research is partially funded by the Interconnect Focus Center (IFC), one of the six focus centers of the Semiconductor Research Corporation (SRC). Fig. 1. Via-ﬁrst TSVs and face-to-back bonding in 3D ICs (side-view). Rectangles (metals) that are attached to the TSVs are TSV landing pads. density [7]–[9], [11]. During ﬁll synthesis, ﬂoating or grounded metal ﬁlls are inserted into layouts so that the feature density in any layout window satisﬁes the feature density constraints. When a layer contains widely varying feature sizes and metal densities, however, dummy ﬁll insertion alone cannot mitigate the topography variation entirely. Moreover, the cumulative effect of the topographic variations for the rest of the eight to twelve interconnect layers signiﬁes the importance of perfect uniformity at the lowest interconnect layer [10]. In this paper we study the impact of TSV landing pads on topography variation, and propose techniques to help minimize the topography variation. II. FINDING OPTIMAL FILL PATTERN Accurate estimation of post-CMP topography requires a time- consuming full-chip CMP simulation because simple mathematical CMP models are inaccurate or simply not available [13]. In addition, M1 feature densities and patterns of 3D ICs are very different from those of 2D ICs. Consequently, it is hard to ﬁnd the optimal ﬁll pattern for each window when TSVs exist in the layout. Therefore, we conduct a DOE similar to the DOE shown in [12] to ﬁnd the optimal ﬁll pattern to minimize the topography variation in 3D ICs. We target selecting a topography-optimal ﬁll using traditional ﬁll methodology. For CMP simulation, we use Calibre CMPAnalyzer [15] with 45nm CMP model provided by Mentor Graphics. The parameters and assumptions used for device process and TSVs are shown in Table I. In this DOE, we create a three-pass ﬁll insertion algorithm, which starts from the largest ﬁll pattern to the smallest ﬁll pattern based on the ﬁll practice in industry [17]. Figure 2 shows an example of three- pass ﬁlling, where Wi and Li are the ﬁll pattern width and length of i-th pass ﬁlling respectively. In each experiment, we choose a ﬁll pattern with the following four parameters: (1) Fill pattern width, (2)