Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies Amit Karel 1 & Mariane Comte 1 & Jean-Marc Galliere 1 & Florence Azais 1 & Michel Renovell 1 Received: 6 March 2017 /Accepted: 21 June 2017 /Published online: 29 June 2017 Abstract Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are likely alternatives to traditional planar Bulk transistors for future technologies due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better elec- trostatic control by the gate over the channel of the transistor. However, FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testabil- ity properties while the impact of defects on circuits imple- mented in FDSOI and FinFET technologies might be signifi- cantly different from the impact of similar defects in planar MOS circuit. It is therefore the objective of the paper to ad- dress this aspect. More specifically, we analyze the electrical behavior of logic gates in presence of a resistive bridging defect for these three different technologies. A particular care has been taken to design transistors and elementary gates in such a way that the comparative analysis in different technol- ogies is meaningful. After implementing similar design in each technology, we compare the electrical behavior of the circuit with the same resistive bridging defect and we analyze both the static and dynamic impact of this defect. Keywords FDSOI . FinFET . Body-biasing . Resistive short defects . Testability 1 Introduction In the past few decades, the transistor feature size is scaling down ceaselessly, confirming the famous Moore’ s law. This unbridled rush towards miniaturization has led to benefits in terms of higher integration, lower energy consumption and better performance. However, these benefits are accompanied by severely increasing short channel effects, process varia- tions and increasing susceptibility to resistive bridging defects due to higher packaging densities [15]. At 28 nm and beyond, the conventional planar bulk transistor has proved to be inad- equate in offering the expected higher performances with low- er power consumption. In order to calculate the impact of transistor scaling on electrical characteristics, MASTAR (Model for Analog and digital Simulation of mos TrAnsistoRs) has been extensively used in ITRS 2005 Process, Integration, Device and Structure report [9, 21]. Figure 1 shows typical values for Drain-Induced Barrier Lowering (DIBL) in Bulk, FDSOI and Double-Gate MOSFETs, as a function of gate length [6]. It is quite evident that at shorter channel length, thin film SOI devices and Double-Gate MOSFETs offers a better electrostatic integrity than the Bulk MOSFETs. Various strain techniques have also been applied to continue the performance growth rate but the boost offered was not in accordance with the increasing manufacturing costs. In order to continue the technology roadmap, the leading industrial communities came up with their respective Responsible Editor: A. D. Singh * Amit Karel amit.karel@lirmm.fr 1 Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM), University of Montpellier /CNRS, 34095 Montpellier, France J Electron Test (2017) 33:515–527 DOI 10.1007/s10836-017-5674-9 # Springer Science+Business Media, LLC 2017