1 Electronic Supplementary Information Sub-kT/q Switching in In 2 O 3 Nanowire Negative Capacitance Field- Effect Transistor Meng Su, a,b Xuming Zou, a Youning Gong, b Jianlu Wang, c Yuan Liu, a Johnny C. Ho, d Xingqiang Liu,* a and Lei Liao* a,b a Key Laboratory for Micro-/Nano-Optoelectronic Devices of Ministry of Education, School of Physics and Electronics, Hunan University, Changsha 410082, China. b School of Physics and Technology, Wuhan University, Wuhan 430072, China. c National Laboratory for Infrared Physics, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China. d Department of Materials Science and Engineering, City University of Hong Kong Tat Chee Avenue, Kowloon, Hong Kong SAR, China. Corresponding author email: liuxq@hnu.edu.cn (Xingqiang Liu); liaolei@whu.edu.cn (Lei Liao). 1. Fabrication of the dual-gated transistor with NW suspending. Fig. S1 Schematic illustrations of the fabrication process of the side-gated In 2 O 3 NC-FETs: (a) A layer of MMA is spin-coated onto the Si/SiO 2 substrate followed by transferring In 2 O 3 NWs; (b) Standard e-beam lithography is applied to define the source, drain and side-gate electrodes; (c) An HfO 2 buffer layer is deposited by ALD; (d) Ferroelectric P(VDF-TrFE) is assembled by spin-coating process at 2000 rpm, and then is baked on the hot plate at 130 °C for 30 min. (e) Fabrication processes in the cross-section view. (f) SEM image of the overall perspective of a double-gate device, the scale bar is 30 nm. The paired gate electrodes are connected by a metal wire. Inset is the SEM image of the device channel; the scale bar is 1 nm. The paired gate electrodes are connected by a metal wire. Electronic Supplementary Material (ESI) for Nanoscale. This journal is © The Royal Society of Chemistry 2018