Frequency and gate voltage effects on the dielectric properties of Au/SiO 2 /n-Si structures _ Ilbilge Dökme a, * ,S ßemsettin Altındal b , Muharrem Gökçen a,b a Science Education Department, Faculty of Education, AhíEvran University, 40100 Kırs ßehir, Turkey b Physics Department, Faculty of Arts and Sciences, Gazi University, 06500 Teknikokullar, Ankara, Turkey article info Article history: Received 25 February 2008 Received in revised form 9 May 2008 Accepted 17 June 2008 Available online 22 June 2008 Keywords: MIS structure Dielectric properties Ac conductivity Electric modulus Frequency dependence abstract To determine the dielectric constant (e 0 ), dielectric loss (e 00 ), loss tangent (tan d), the ac electrical conduc- tivity (r ac ) and the electric modulus of Au/SiO 2 /n-Si structure, the measurement admittance technique was used. Experimental results show that the values of e 0 , e 00 , tan d, r ac and the electric modulus show fairly large frequency and gate bias dispersion especially at low frequencies due to the interface charges and polarization. An increase in the values of the e 0 and e 00 were observed with both a decrease in fre- quency and an increase in frequency. The r ac is found to increase with both increasing frequency and voltage. In addition, the experimental dielectrical data have been analyzed considering electric modulus formalism. It can be concluded that the interface charges and interfacial polarization have strong influ- ence on the dielectric properties of metal–insulator–semiconductor (MIS) structures especially at low fre- quencies and both in depletion and accumulation regions. Ó 2008 Elsevier B.V. All rights reserved. 1. Introduction The metal–insulator–semiconductor (MIS) structures or metal– oxide–semiconductor (MOS) consist of an insulator layer between metal and semiconductor. This insulator layer cannot only prevent inter-diffusion between metal and semiconductor substrate, but also alleviate the electric field reduction issue in these structures. An insulator layer in these structures gives these devices the prop- erties of a capacitor, which stores the electric charge, by virtue of the dielectric properties of oxide layers. The presence of interfacial insulator layer and interface states at M/S interface strongly influ- ences both the electrical and dielectric behavior of these struc- tures. The formation of an insulator layer on Si by traditional ways of oxidation or deposition cannot completely passivate the active dangling bonds at the semiconductor surface. At high angu- lar frequencies (x =2pf), the carrier life time s is much larger than the period (T = 1/x), the charges at the interface states cannot fol- low an ac signal. In contrary, at low frequencies the charges can easily follow an ac signal and so the effect of these charges on the capacitance of devices increases with decreasing frequency. Therefore, the frequency dependent electrical and dielectric char- acteristics are very important according to accuracy and reliability result [1–13]. When localized interface states exist at the Si/SiO 2 interface and the device behavior is different from the ideal case due to their presence. These interface states usually cause a bias shift and frequency dispersion of the C–V and G–V curves [14]. Therefore, it is important to include the effect of the frequency and examine in detail the frequency dispersion of dielectric prop- erties. The frequency response of the dielectric constant (e 0 ), dielec- tric loss (e 00 ) and dielectric tangent (tan d) is dominated by a low frequency dispersion, whose physical origin has long been in ques- tion [7]. In our previous work [15], we investigated the frequency dependence of the forward and reverse bias C–V and G/w–V char- acteristics of Au/SiO 2 /n-Si structures at room temperature. The aim of this study is to investigate the effect of the frequencies and gate bias on dielectric properties of MIS structures by using the forward and reverse bias admittance measurements over the frequency and gate bias range of 1 kHz–1 MHz and 8 V to 8 V, respectively. Experimental results show that the dielectric proper- ties have been found a strong function of frequencies and bias voltage. 2. Experimental procedure The metal–insulator–semiconductor (Au/SiO 2 /n-Si) structures used in this study were fabricated using n-type (Phosphor-doped) single crystal silicon wafer with <1 0 0> surface orientation, having thickness of 280 lm, 2 00 diameter and 8 X cm resistivity. For the fabrication process, Si wafer was degreased in organic solvent of CHClCCl2, CH3COCH3 and CH3OH, etched in a sequence of H2SO4 and H2O2, 20% HF, a solution of 6HNO3:1HF:35H2O, 20% HF and finally quenched in de-ionized water of resistivity of 0167-9317/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2008.06.009 * Corresponding author. Tel.: +90 3122155471; fax: +90 382134513. E-mail address: ilbilgedokme@gazi.edu.tr ( _ I. Dökme). Microelectronic Engineering 85 (2008) 1910–1914 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee