80 nm gate-length Si=Si 0.7 Ge 0.3 n-MODFET with 194 GHz f max S.J. Koester, K.L. Saenger, J.O. Chu, Q.C. Ouyang, J.A. Ott, M.J. Rooks, D.F. Canaperi, J.A. Tornello, C.V. Jahnes and S.E. Steen DC and RF performance of scaled n-channel Si=SiGe modulation- doped field effect transistors (n-MODFETs) grown by ultra-high vacuum chemical vapour deposition is reported. Devices with source-to-drain spacing of 300 nm, and gate length of 80 nm (70 nm) displayed f max ¼ 194 GHz (175 GHz) and f T ¼ 70 GHz (79 GHz). Introduction: Si=SiGe MODFETs are potentially attractive devices for high-speed, low-noise communications applications, where low cost and compatibility with CMOS logic technology are desirable. Much of the recent work on Si=SiGe n-MODFETs has utilised layer structures grown by molecular beam epitaxy (MBE) [1, 2]. However, ultra-high vacuum chemical vapour deposition (UHV-CVD) is also an attractive growth technique since it is a well-established manufactur- ing technology already used for SiGe HBTs [3] and several key demonstrations of n-MODFETs using UHV-CVD grown layers have already been made [4, 5]. Both vertical and lateral scaling are key to obtaining high performance in MODFETs [6], but vertical scaling of n-MODFETs grown by UHV-CVD is complicated by the difficulty of achieving abrupt phosphorus profiles [7]. In this Letter, we demon- strate Si=SiGe n-MODFETs fabricated on vertically-scaled layer structures grown by UHV-CVD that also have aggressively-scaled lateral dimensions. In particular, we demonstrate MODFETs with 80 nm gate length and source-to-drain spacing of 300 nm that have f max values as high as 194 GHz. To our knowledge, this is the highest f max reported to date for a Si=SiGe MODFET. Fabrication: The modulation-doped heterostructure utilised in the present work was grown on a lightly-doped p-type 8 inch Si wafer by UHV-CVD. The layer structure consisted of an SiGe buffer layer, step-graded to an Ge alloy-content of approximately 30%, followed by a strained Si quantum well, an Si 0.7 Ge 0.3 spacer layer, an Si 0.7 Ge 0.3 supply layer with abrupt phosphorus doping, and an Si cap layer. The total distance between the top of the Si quantum well and the surface, d QW , was about 15 nm. This is considerably less than the typical distance of 25 nm used in previous work [5], and is essential for gate- length scaling beyond 100 nm [6]. The room-temperature electron sheet density and mobility, as determined by van der Pauw measure- ments, were 2.2  10 12 cm 2 and 1700 cm 2 =Vs, respectively. The device fabrication started with the formation of planar shallow- trench isolation, followed by implantation of phosphorus at 12 keV and activation at 700  C to form the source and drain regions. Next, NiSi contacts were formed by deposition of Ni and annealing at 500  C. T- shaped Schottky gates were then defined using electron-beam lithogra- phy and lift-off of Ir=Ti=Au (20=20=180 nm) metallisation. Ir was used as the Schottky contact instead of Pt due to its higher barrier height and better thermal stability. Finally Ti=Au (20=330 nm) pad metallisation was deposited. Two sets of devices, A and B, with different gate contact schemes were fabricated. On sample A, the probe contact for the gate electrode was formed as part of the pad metallisation level, and thus had to overlap the T-gate metallisation in order to make contact with the gate. On sample B, the gate probe contact was fabricated as part of the T-gate metallisation, so that the T-gate and the gate pad consisted of a continuous piece of metal. Results: DC characterisation of the devices was carried out using an HP4145B semiconductor parameter analyser at room temperature. The devices from samples A and B had very similar DC I–V characteristics. Figs. 1a and b show typical output and transconduc- tance characteristics, respectively, for a device on sample B with gate length, L g , of 80 nm and source-to-drain implant spacing, L ds , of 300 nm. The small value of L ds allowed the devices to have high drive current of 230 mA=mm at gate-to-source and drain-to-source voltages of V gs ¼þ0.6 V and V ds ¼þ1.5 V, respectively. However, the small L ds also leads to considerable parasitic off current (10 mA=mm at V gs ¼ 0.8 V). The average peak transconductance, g m , was 240 mS=mm at V ds ¼þ1 V, while the output conductance under the same bias conditions had an average value of 36 mS=mm, leading to a maximum DC voltage gain, A v  g m =g d , of 6.6. The devices had very low gate leakage; at V gs ¼1 V and V ds ¼þ1 V, the gate current, I g , was only 10 mA=mm, and I g was more than five orders of magnitude lower than the drain current at the bias condition for peak g m . Fig. 1 Output characteristic and transconductance characteristic a Output characteristic for Si=SiGe n-MODFET from sample B with L g ¼ 80 nm V gs range is þ0.6 to 0.5 V, with increment of 0.1 V b Transconductance characteristic for same device as in a at V ds values of þ0.4 and þ1.0 V Fig. 2 jh 21 j 2 and Mason’s unilateral gain (MUG) against frequency for Si=SiGe n-MODFET from sample B with L g ¼ 80 nm at V gs ¼0.1 V and V ds ¼þ1.5 V j jh 21 j 2 s MUG —— 20 dB=decade extrapolation of jh 21 j 2 ––– 20 dB=decade extrapolation of MUG S-parameters were measured against frequency on devices from both samples with two-finger device geometries and total gate width of 20 mm. De-embedding of the pad parasitics was accomplished using open- and short-circuit geometries. Fig. 2 shows the de-embedded forward current gain, jh 21 j 2 , and Mason’s unilateral gain (MUG) plotted against frequency for the best 80 nm gate-length device from sample B biased at V gs ¼0.1 V and V ds ¼þ1.5 V. Both jh 21 j 2 and MUG exhibited nearly-ideal roll off, and extrapolation at 20 dB=decade produced values of f T ¼ 70 GHz and f max ¼ 194 GHz. The devices from sample A had slightly shorter gate length of 70 nm and exhibited similar roll-off behaviour to devices from sample B. The best device on sample A exhibited f T of 79 GHz and f max of 175 GHz at ELECTRONICS LETTERS 13th November 2003 Vol. 39 No. 23