Superpage-Friendly Page Table Design for Hybrid Memory Systems Xiaoyuan Wang 1,2,3,4 , Haikun Liu 1,2,3,4(&) , Xiaofei Liao 1,2,3,4 , and Hai Jin 1,2,3,4 1 National Engineering Research Center for Big Data Technology and System, Huazhong University of Science and Technology, Wuhan 430074, China {xiaoyuanw,hkliu,xfliao,hjin}@hust.edu.cn 2 Service Computing Technology and System Lab, Huazhong University of Science and Technology, Wuhan 430074, China 3 Cluster and Grid Computing Lab, Huazhong University of Science and Technology, Wuhan 430074, China 4 School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, China Abstract. Page migration has long been adopted in hybrid memory systems comprising dynamic random access memory (DRAM) and non-volatile mem- ories (NVMs), to improve the system performance and energy ef ficiency. However, page migration introduces some side effects, such as more translation lookaside buffer (TLB) misses, breaking memory contiguity, and extra memory accesses due to page table updating. In this paper, we propose superpage- friendly page table called SuperPT to reduce the performance overhead of serving TLB misses. By leveraging a virtual hashed page table and a hybrid DRAM allocator, SuperPT performs address translations in a flexible and ef fi- cient way while still remaining the contiguity within the migrated pages. Keywords: Page table Á Hybrid memory system Á Page migration Á Multiple page sizes Á Address translation 1 Introduction Recent years have witnessed many large-footprint applications. Traditional DRAM- based memory systems are unable to meet the ever-increasing memory demand due to the limited DRAM scaling in terms of memory density and power ef ficiency. The advent of non-volatile memory (NVM) technologies has attracted a lot of interests in constructing large-capacity and energy-ef ficient main memory systems with NVMs. However, since NVM cannot directly replace DRAM due to its shortcomings, such as lower performance and limited write endurance, hybrid memory systems composed of DRAM and NVM have been widely studied [1–4]. Most of these studies make efforts to improve system performance and save energy by using page migration [4, 5]. As the amount of memory required by applications increase significantly, the number of page table entries (PDEs) also grows rapidly. However, the capacity of Translation Lookaside Buffer (TLB) which is used to cache virtual-to-physical address © Springer Nature Singapore Pte Ltd. 2020 J. Zeng et al. (Eds.): ICPCSEE 2020, CCIS 1257, pp. 623–641, 2020. https://doi.org/10.1007/978-981-15-7981-3_46