Noname manuscript No. (will be inserted by the editor) An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division Manish Kumar Jaiswal · Hayden K.-H. So Received: date / Accepted: date Abstract A hardware architecture for quadruple precision floating point division arithmetic with multi-precision support is presented. Division is an important yet far more complex arithmetic operation than addition and multiplication, which demands significant amount of hardware resources for a complete implementation. The pro- posed architecture also supports the processing of single, double and double-extended precision computations with varied latency. An iterative multiplicative-based archi- tecture for multi-precision quadruple precision division is proposed with small size and promising performance. The proposed mantissa division architecture, the most complex sub-unit, employs a series expansion methodology of division. The archi- tecture follows the standard state-of-the-art flow for floating point division arithmetic with normal as well as sub-normal processing. The proposed division architecture is synthesized using UMC 90nm ASIC standard cell library. It is also demonstrated using a Xilinx FPGA based implementation which is integrated with a wide integer multiplier for mantissa division further optimized for FPGA implementations facili- tating the built-in DSP blocks efficiently. When compared to existing quadruple pre- cision divider available in the literature, the proposed architecture has 25% equivalent area saving, 2x improvement in latency with improved speed on FPGA platform; and it has more than 50% area saving, 3x improvement in latency-throughput with better speed on ASIC platform. Keywords Quadruple Precision Arithmetic · Division · ASIC · FPGA · Iterative Architecture · Multi-Precision Division · Digital Arithmetic This work is partly supported by the Research Grants Council of Hong Kong (Project GRF 17245716), and the Croucher Foundation (Croucher Innovation Award 2013). Manish Kumar Jaiswal Department of EEE, The University of Hong Kong, Hong Kong. E-mail: manishkj@eee.hku.hk, man- ishkj25@gmail.com Hayden K.-H. So Department of EEE, The University of Hong Kong, Hong Kong. E-mail: hso@eee.hku.hk