FPGA Implementation of a PWM for a Three-Phase DC–AC Multilevel Active-Clamped Converter Emili Lupon, Sergio Busquets-Monge, Senior Member, IEEE, and Joan Nicolas-Apruzzese, Student Member, IEEE Abstract—With the aim to implement a suitable controller for a three-phase dc–ac multilevel active-clamped converter to enable its use in practice, and as a first step toward a full closed-loop converter control implementation into a single field-programmable gate array (FPGA) device, this paper presents the structure and features of an FPGA implementation of an appropriate pulsewidth modulation (PWM) strategy. The selected PWM strategy guarantees dc-link capacitor voltage balance in every switching cycle, and covers both the undermodulation and overmodulation regions. A flexible im- plementation is conceived, allowing the variation of important operating parameters, such as the modulation index and switching frequency, through a simple user interface. The key aspects to achieve an efficient and robust FPGA implementation are discussed. Experimental results in a four-level converter prototype controlled with an Altera Cyclone III device under different operating condi- tions match fairly well with the expected results obtained through simulation, thus verifying the accurate performance of the FPGA- based modulator. Index Terms—Field-programmable gate array (FPGA), multilevel active-clamped (MAC) converter, pulsewidth modulation (PWM). I. INTRODUCTION P OWER ELECTRONICS converter technology evolves toward multilevel topologies with higher number of switch- ing devices, higher switching frequencies to obtain higher power density and better dynamic performance, and increased control complexity. One of such topologies is the recently proposed multilevel active-clamped (MAC) topology [1], shown in Fig. 1 (a) for a four-level case, which is built upon a single controlled switching semiconductor device with an antiparallel diode. The functional model of the converter leg is the same as for a diode- clamped converter: a single-pole four-throw switch that connects the output leg terminal to one of the four input leg terminals through the application of the corresponding switching state. Fig. 2 presents these switching states for a four-level converter leg. The uncircled switches are off-state devices. The circled switches are on-state devices. The solid-line circled switches connect the output terminal to the desired input terminal and conduct the output terminal current ( ). The dotted-line-circled switches do not conduct any significant current and simply clamp the blocking voltage of the off-state devices to the voltage across adjacent input terminals ( ). Compared to a multilevel diode- clamped converter, which presents a lower controlled switch count, the active-clamped topology’s advantages are [1] lower conduction loss, better distribution of switching losses, device blocking voltage always equal to one dc-link capacitor voltage, and increased fault-tolerance capacity. Motor drives, in particu- lar the traction inverter of electric vehicles, is one of the applications where the MAC topology could bring benefits. For this purpose, three legs can be connected to a common dc-link to obtain a four-level three-phase active-clamped converter shown in Fig. 1(b). However, in order to take full advantage, in practice, of the topology benefits, a robust and efficient controller has to be developed at a reasonable cost and with reduced complexity. This is the final goal of the present study. Power converter control has been progressively migrating from the analog to the digital domain [2]. With the improvement of digital control devices and control techniques, in many applications, the inherent drawbacks of digital control (i.e., finite resolution leading to a reduced accuracy and the need of sampling and processing time leading to delays) have been compensated by the following advantages: 1) increased control complexity; 2) flexibility; 3) repeatability; 4) reliability; 5) versatility; and 6) expandability. Typical power converter digital controllers are based on microprocessors (μ ), digital signal processors (DSPs), field- programmable gate arrays (FPGAs), or a combination of them. μ and DSPs contain a central processing unit (CPU, fixed hardware) in charge of sequentially processing a set of instruc- tions. They are, therefore, known to be software-programmable. Microcontrollers and digital signal controllers embed the μ or DSP core, memory, and input/output peripherals (including PWM units) in the same chip. The programming can be per- formed with high-level algorithmic languages familiar to most designers. FPGAs [3] basically contain an array of logic elements or cells (each cell containing look-up tables and registers), whose interconnections are decided by the contents of a random- access memory (RAM). The FPGA design, typically using hardware description languages, decides the final circuit struc- ture to achieve a desired functionality, and it is, therefore, said to be hardware-programmable. Besides a large number of configurable input/output blocks, FPGAs also typically contain additional optimized RAM blocks and multipliers to increase the performance of the device. Logic, adders, subtractors, comparators, multipliers, and special functions are easy to implement in these typical FPGAs. Special functions are im- plemented using look-up tables in RAM blocks. However, Manuscript received July 04, 2013; revised November 12, 2013 and January 27, 2014; accepted February 19, 2014. Date of publication March 03, 2014; date of current version May 02, 2014. This work was supported by the Ministerio de Ciencia e Innovación, Spain, under Grant CSD2009-00046. Paper no. TII-13- 0438. The authors are with the Department of Electronic Engineering, Technical University of Catalonia, 08028 Barcelona, Spain (e-mail: emili.lupon@upc.edu; sergio.busquets@upc.edu; joan.nicolas@upc.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TII.2014.2309483 1296 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 10, NO. 2, MAY 2014 1551-3203 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.