95 0740-7475/00/$10.00 © 2000 IEEE July-September 2000 IEEE STD 1394, 1 referred to as FireWire, is one of the most widely accepted solutions to the growing need for mass information transfer among computers, storage devices, printers, dig- ital video/audio devices, and so on. It consists of a hardware and software standard for transport- ing digital data at up to 400 megabits per second today and 800 Mbps or more in the future. IEEE 1394 provides two types of data transfer: asyn- chronous and isochronous. Asynchronous data transmission, the traditional method for trans- mitting data between computers and peripher- als, is used for nodes not requiring a precise timing reference. Isochronous data transfer pro- vides data transport at a predetermined rate 1 and is especially important for real-time digital mul- timedia applications in consumer electronics. We designed a 1394 physical layer (phy- layer) and physical-link interface (PHY-LINK) integrated-circuit core, targeting a transmission rate of 400 Mbps and more. Design develop- ment began with a behavioral VHDL descrip- tion based on the 1394 specifications. We used the VHDL model to simulate the protocol fea- tures and performance. This phase required a large debugging effort to correct inconsistencies in the standard documentation. We subscribed to the official 1394 Trade Association mailing list (www.STDS-1394@IEEE.org) and participated in discussions concerning possible modifica- tions to the standard documentation. As a result, we obtained a product compliant with the IEEE 1394a standard specification. 2 The second part of the project entailed devel- oping a structural VHDL description of the core and synthesizing it to the gate level by means of a standard logic synthesizer (Synopsys, version 3.5a). The design is intended as a reusable intel- lectual property (IP) that can be mapped to any customer’s technology and included in a larger custom design. Targeting the phy-layer and PHY-LINK allowed our design to have the broad- est range of reusability, because it does not include application-dependent features. To establish a performance evaluation, we mapped the gate-level netlist on industrial, fully static, 0.35-micron CMOS standard-cell technology (Corelib HCMOS6 from ST Microelectronics). Finally, we tested the project through gate-level simulations based on the extracted postlayout parasitics in standard delay format (SDF). This article describes the architecture and the hardware design solutions we used to satis- fy the IEEE 1394a specifications. 2 Several 1394 Trade Association 3 members have devised other interesting commercial products: Semicustom Design of an IEEE 1394-Compliant Reusable IC Core In 0.35-micron standard-cell CMOS technology, this IC core design supports a data rate of up to 400 Mbps and includes circuit blocks that operate at a clock frequency of 400 MHz. Mauro Bertacchi ST Microelectronics Alessandro De Gloria University of Genoa Daniele Grosso Cadence Design Systems Mauro Olivieri University of Rome “La Sapienza”