Journal of VLSI Signal Processing 41, 169–182, 2005 c  2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands. MPARM: Exploring the Multi-Processor SoC Design Space with SystemC LUCA BENINI AND DAVIDE BERTOZZI DEIS—University of Bologna, Via Risorgimento 2, Bologna, Italy ALESSANDRO BOGLIOLO ISTI—University of Urbino, Piazza della Repubblica, 13 Urbino, Italy FRANCESCO MENICHELLI AND MAURO OLIVIERI DIE—La Sapienza University of Rome, Via Eudossiana 18, 00184 Roma, Italy Received February 13, 2003; Revised December 24, 2003; Accepted July 30, 2004 Abstract. Technology is making the integration of a large number of processors on the same silicon die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a high degree of flexibility and represent the most efficient architectural solution for supporting multimedia applications, characterized by the request for highly parallel computation. As a consequence, tools for the simulation of these systems are needed for the design stage, with the distinctive requirement of simulation speed, accuracy and capability to support design space exploration. We developed a complete simulation platform for a MP-SoC called MP-ARM, based on SystemC as modelling and simulation environment, and including models for processors, the AMBA bus compliant communication ar- chitecture, memory models and support for parallel programming. A fully operating linux version for embedded systems has been ported on this platform, and a cross-toolchain has been developed as well. Our MP simulation environment turns out to be a powerful tool for the MP-SOC design stage. As an example thereof, we use our tool to evaluate the impact on system performance of architectural parameters and of bus arbitration policies, showing that the effectiveness of a particular system configuration strongly depends on the application domain and the generated traffic profile. Keywords: system-on-chip simulation, multiprocessor embedded systems, design space exploration 1. Introduction Systems-on-chips (SoC) are increasingly complex and expensive to design, debug and fabricate. The costs in- curred in taking a new SoC to market can be amortized only with large sales volume. This is achievable only if the architecture is flexible enough to support a number of different applications in a given domain. Processor- based architectures are completely flexible and they are often chosen as the back-bone for current SoCs. Multi-media applications often contain highly parallel computation, therefore it is quite natural to envision Multi-processor SoCs (MPSoCs) as the platforms of choice for multi-media. Indeed, most high-end multi- media SoCs on the market today are MPSoCs [1–3]. Supporting the design and architectural exploration of MPSoCs is key for accelerating the design process and converging towards the best-suited architectures for a target application domain. Unfortunately we are today in a transition phase where design tuning, opti- mization and exploration is supported either at a very high-level or at the register-transfer level. In this pa- per we describe a MPSoC architectural template and a simulation-based exploration tool, which operates at the macro-architectural level, and we demonstrate its usage on a classical MPSoC design problem, i.e., the