Electrical Characterization Methodologies for the Assessment of High- Gate Dielectric Stacks Chadwin D. Young, Gennadi Bersuker, Dawei Heh, Arnost Neugroschel, Rino Choi, Chang Yong Kang, Joey Tun * , and Byoung Hun Lee † SEMATECH, 2706 Montopolis Drive, Austin, TX 78741 * Keithley Instruments, Inc., 28775 Aurora Rd, Cleveland, OH, 44139 † IBM Assignee to SEMATECH Various conventional and novel electrical characterization techniques have been combined with comprehensive analysis to properly evaluate high- gate dielectric stack structures. These measurement methodologies and analysis techniques are intended to separate contribution from the pre-existing defects, which may serve as charge traps, from the stress-generated defects. In addition, the differentiation of electrically active bulk high- traps and interfacial layer traps has been demonstrated. Introduction Hafnium-based dielectrics are being widely investigated as potential candidates for the gate dielectric in advanced gate stacks. Significant progress has been made in fabricating high- gate stack transistors meeting ITRS requirements for low equivalent oxide thickness (1.0 nm), low leakage current (1-10 A/cm 2 ) and high mobility (90% of SiO 2 ) [1]. Performance improvements were achieved via precise engineering of the gate stack resulting in reduced charge trapping and enhanced carrier mobility, although bias temperature instability (BTI) still remains an issue affecting device life time [2]. Specific features of high- gate stacks, in particular, its multi-layer structure and high density of as-grown structural defects in the transition metal oxides [3] complicates the evaluation of their intrinsic electrical characteristics and reliability. Pre-existing defects, some representing electron traps, give rise to the fast transient charging (FTC) phenomenon [4], which is shown to cause threshold voltage instability and mobility degradation [5]. The presence of the SiO 2 layer at the interface between the hafnium- based dielectric and the substrate, the properties of which can be affected by the specifics of the gate stack fabrication process, makes it more difficult to identify the location and origin of the stress-generated fixed charges and electron/hole traps. Therefore, correct assessments of the advanced gate stack properties call for both novel measurement techniques, such as pulsed current-voltage (I-V) measurements [6-9], as well as thorough analysis and careful data interpretation of conventional electrical characterization techniques, in particular frequency-dependent charge pumping, DCIV, and TDDB. In this work, we provide an overview of various techniques with respect to their application to high- gate stack characterization. ECS Transactions, 11 (4) 335-346 (2007) 10.1149/1.2779572 ©The Electrochemical Society 335 Downloaded 20 Jun 2012 to 203.230.49.158. Redistribution subject to ECS license or copyright; see http://www.ecsdl.org/terms_use.jsp