This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON ELECTRON DEVICES 1 Demonstration of 40-nm Channel Length Top- Gate p-MOSFET of WS 2 Channel Directly Grown on SiO x /Si Substrates Using Area-Selective CVD Technology Yun-Yan Chung, Kuan-Cheng Lu, Chao-Ching Cheng , Ming-Yang Li, Chao-Ting Lin, Chi-Feng Li , Jyun-Hong Chen, Tung-Yen Lai, Kai-Shin Li, Jia-Min Shieh , Sheng-Kai Su, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li, H.-S. Philip Wong, Fellow, IEEE, Wen-Bin Jian, and Chao-Hsin Chien Abstract — For high-volume manufacturing of 2-D tran- sistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have success- fully grown continuous and uniform WS 2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the trans- mission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS 2 channels on SiO x /Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10 6 , a subthresh- old swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL). Index Terms— Area selective chemical reaction deposition (CVD), p-MOSFET, short channel device, tungsten disulfide, WS 2 . I. I NTRODUCTION S EMICONDUCTOR technology scaling continues to push the limits of materials and processes in order to achieve high performance with a lower power consumption of logic function. However, mature silicon devices have been Manuscript received July 2, 2019; revised August 27, 2019; accepted October 3, 2019. This work was supported by Grant MOST-107-2221-E-009-095-MY3 and Grant MOST-108-3017-F-009- 003. The review of this article was arranged by Editor E. Pop. (Corresponding authors: Chao-Ching Cheng; Chao-Hsin Chien.) Y.-Y. Chung, C.-T. Lin, C.-F. Li, and C.-H. Chien are with the Department of Electronics Engineering and the Institute of Electron- ics, National Chiao Tung University, Hsinchu 30010, Taiwan (e-mail: chchien@faculty.nctu.edu.tw). K.-C. Lu and W.-B. Jian are with the Department of Electro Physics, National Chiao Tung University, Hsinchu 30010, Taiwan. J.-H Chen, T.-Y. Lai, K.-S. Li, and J.-M Shieh are with the National Applied Research Laboratories, Taiwan Semiconductor Research Insti- tute, Hsinchu 30078, Taiwan. C.-C. Cheng, M.-Y. Li, S.-K. Su, H.-L. Chiang, T.-C. Chen, L.-J. Li, and H.-S. P. Wong are with the Corporate Research, Taiwan Semi- conductor Manufacturing Company, Hsinchu 30077, Taiwan (e-mail: chengcca@tsmc.com). Color versions of one or more of the figures in this article are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2019.2946101 confronted with many challenges, in particular, achieving good electrostatic control for transistors of future 3-nm technology node and beyond. 2-D materials [1], such as transition metal dichalcogenides (TMDs), provide a pathway to achieving high device performance at short gate lengths due to high carrier mobility in the ultrathin channel with suppressed short channel effects [2]. In recent years, the n-FETs based on chemical reaction deposition (CVD)-grown MoS 2 have been shown to have good performance [3]–[8]. However, there were few demonstrations of TMD p-FETs with competitive performance due to more challenges in film growth for p-type transistors and dopant control on SiO x /Si substrates. In this article, we use a metal-assisted CVD method to form the area-selective WS 2 channel on SiO x /Si substrates. Smooth WS 2 channel thickness of about 4.9 nm was demonstrated, and the underlying growth mechanisms were also inferred. The device performance of the fabricated top-gated p-FETs of CVD-WS 2 is competitive with the n-FETs of CVD-MoS 2 reported in the literature. Area-selective CVD growth is a promising approach for high volume manufacturing of high- performance 2-D transistors because it eliminates the need for 2-D material layer transfer over the wafer-scale area with high uniformity. In Fig. 1, we present the intrinsic ON-current ( I ON ) of a double-gate transistor with an ultrathin channel (1 nm) calcu- lated using the top of the barrier model. The details of device simulation can be found in [9]. The backscattering effect and the direct source to drain tunneling leakage are included in the simulation. Effective mass along the channel direction and mobility are good indexes for the ballistic velocity and ballistic ratio, respectively. The resultant I ON contour map of 1 nm-thin channel devices for a gate length of 7 nm is plotted in Fig. 1. Note that intrinsic I ON is compared at V DD = 0.6 V after the alignment to the same I OFF value of 10 -4 μA/μm. From simulation results, it is clear that the channel materials should have appropriate and effective mass, and large carrier mobility to achieve the highest I ON in devices. For materials with a larger effective mass, e.g., >0.2 m 0 , the I ON starts to degrade due to a smaller ballistic velocity, 0018-9383 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. 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