732 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 31, NO 5, MAY 1996 On-Chip zyxwvut ZDDe Testability Schemes for Detecting Multiple Faults in CMOS IC’s Changku Hwang, Mohammed Ismail, and Joanne E. DeGroat o SUB-BLOCK1 -T zyxwvutsr 0 0 zyxwvu Abstract-In this paper we present two on-chip design-for- testability (DFT) schemes for CMOS IC’s. One is for small cir- cuits and the other for large circuits. Both schemes identify a faulty area on a chip with only a small area overhead for the additional circuitry and at most two extra pins. Moreover, if faults occur in different areas, multiple faults can also be de- tected with the proposed schemes. To demonstrate the ideas, DFT is incorporated in a 4-bit carry look ahead adderlsubtrac- tor (CLAAS) as well as a 16-bit arithmic logic unit (ALU). Sim- ulation results are given. I. INTRODUCTION T is well known that an analog fault which produces no logical error cannot be detected with a stuck-at test set. However, analog faults must be considered in chip testing since they degrade circuit performance and have the po- tential to become logical faults that generate a logical er- ror [I], [2]. Furthermore, an analog fault leads to other abnormalities. One such abnormality is the current flow from power lines to GND in steady state response given a certain input test pattern. Detecting such current flow in the faulty location is the concept behind the quiescent power current testing (IDDQ) method [l], [3]-[8]. One of many current testing methodologies which detect such current is the distributed testing logic (DTL) [l]. It re- quires test patterns only for activation of faults [I], [9], but not for fault propagation [IO] and requires no sub- stantial modification in the circuit under test. Such mod- ifications may put severe constraints on design styles and could prevent circuit optimization zyxwvutsr [ 111. However, as pointed out in [7], the scheme in [ 11 requires a large num- ber of extra transistors as each gate needs two extra tran- sistors. Another inherent limitation of VLSI testing is that it is impossible to observe certain nodes directly because of the complexity of modem VLSI circuits. So far very few on-chip VLSI testing schemes have been introduced which attempt to isolate the fully area. Most of the DFT schemes developed, e.g., [l], [7] only test whether or not the chip has a fault, but cannot locate the fault or even the faulty area. Manuscript received September 1, 1992; revised September 15, 1995. This work was supported in part by the Norwegian Research Council and in part by the Nokia Foundation. The authors are with the Department of Electrical Engineering, Ohio State University, Columbus, OH 43210 USA. M. Ismail is on leave as a Fulbright-Hays Visiting Professor at the Helsinki University of Technol- ogy, Espo, Finland. Publisher Item Identifier S 0018-9200(96)03399-9. I SUB-BLOCK N Fig. 1. The proposed Scheme 1 NOR Sensing Gate This paper proposes two DFT schemes that can detect faulty areas with only a small amount of extra area over- head and at most two extra pins. The first scheme, sug- gested for detecting faults in a small circuit, is an im- proved version of the schemes reported in [l] and [7], while the second is a new scheme for detecting faults in a large circuit. 11. PROPOSED DFT SCHEMES zyx A. Scheme zyxwv 1 Scheme 1 is illustrated schematically in Fig. 1. The en- tire design is divided into n SUBBLOCKS (SB) where n equals the number of outputs. Each SB is modified by inserting a n-channel MOSFET (N,) for detecting the ex- cessive current between GND and the n-channel network. In most cases, however, each SB should be divided into several small sub-blocks (SSB) each containing a number of logic gates. This reduces the resistive noise coupling [12] and the potential for changing the dynamic perfor- mance of the chip at the virtual ground (VG) during the normal chip operation. The partitioning of the device de- pends on its configuration. The NOR sensing gate [designed with a p-channel pull- up MOSFET zyxwv (Pi) and n-channel pull-down MOSFET’s (N2)] should be designed as static ratioed logic. The size of N2 should be small because of the following reasons: small capacitive noise coupling [ 121, fast operation in test mode, and small area overhead. The output of the exces- sive current detecting circuitry is composed of two stage NOR gates. NOR1 and NOR2 are driven by the control 0018-9200/96$05,00 0 1996 IEEE