Power optimization in current mode circuits M. S. Bhat and H. S. Jamadagni Centre for Electronics Design and Technology Indian Institute of Science, Bangalore-560012, INDIA {msbhat, hsjam}@cedt.iisc.ernet.in Abstract We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present an approximation model for current in a current comparator circuit. Power reduction is achieved through turning off the redundant comparator circuits using a switch-architecture. Simulations are carried- out for current-mode flash ADC designs and literal generating circuits for MVL. We show that the simple switch architecture with minimum area overhead can be used to trade-off power dissipation with delay in these designs. 1. Introduction Wide spread interest in wireless communication and portable computing has created a critical need for low-power low-voltage analog and digital integrated circuits. The three components of power dissipation in CMOS logic are switching, static (or leakage) and short-circuit. Of the three components, the dominant component in analog and multiple-valued logic circuits being static power dissipation. Therefore, static power reduction is an important optimization constraint in analog and MVL circuit design. Current-mode circuit techniques, which process the active signals in the current domain, offer a number of advantages [1]. Current comparator is a fundamental component of current-mode analog integrated circuits. A critical design aspect for comparator is good trade- off between sensitivity, speed and power dissipation. Speed, in fact, can usually be increased at the expense of higher power consumption, while sensitivity requires high gain and hence low bias current, which leads to a slower time response. In the last decade, several comparator architectures have focused to address some of these issues [2]-[5]. When circuits employ a set of comparators for purposes such as those in flash ADC and literal based multiple-valued logic modules, the comparator set generates a thermometer code that reflects the input signal amplitude. As the input signal amplitude increases, more and more comparators are turned on thereby establishing a large static current from power supply to ground. Since we are interested in the outputs of only those comparators whose output changes from zero to one for the given input, we can, in principle, turn-off many of the comparators whose outputs are already high and that they do not contribute any information to the final digital value. This can be accomplished by introducing switches at appropriate places to turn off the current drawn by such comparators without affecting the final output value. The approach is analogous to selective signal gating in digital circuits. 2. Power dissipation in current comparators It is a well-understood fact that the power dissipated in a digital circuit can be expressed as 2 . .. . . .. . DD sc peak DD leakage DD P CV f t I V f I V (1) where C f , , and sc t are the total switching capacitance, clock frequency, switching activity factor and the time during which a short circuit exists between supply and ground respectively. The three terms on the right hand side of (1) correspond to dynamic power, short-circuit power and leakage power respectively In the case of analog circuits, the dynamic power component and the associated short circuit power components are far too small compared to the static component. The static power dissipation is again due to two terms, one resulting from the finite resistance Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE