International Journal of Computer Applications (0975 – 8887) Volume 184– No.23, July 2022 12 High Speed Compressor based Adder using XOR-XNOR Gate: A Study Monika Singh Research Scholar Department of Electronics & Communication Engineering, Lakshmi Narain College of Technology, Bhopal, India Prashant Chaturvedi Professor Department of Electronics & Communication Engineering, Lakshmi Narain College of Technology, Bhopal, India ABSTRACT Multiplier is an essential block of a computing device. Multipliers are commonly used for signal and image processing applications where multipliers are used to perform various tasks like convolution, correlation and filtering. Multipliers are not only a high delay component but also dissipate high amount of power. It is necessary to increase the speed of multipliers as the demand of high speed processors is increasing. Moreover, multipliers is an integral part of any processor and are utilized by the processors to complete signal processing tasks. Optimizing performance of multipliers provides better results in digital signal processors. In multiplier, reduction of partial products takes more time and consumes high power. A huge number of adders are used to perform the partial product reduction operation. Optimizing the partial products reduction is a challenging task for researchers. Compressors take more inputs at a time and are able to process partial products in a faster way compared to conventional adders. Use of compressors in the partial product reduction helps to minimize the delay but not power consumption. Keywords Compressor, Compressor Based Adder, XOR-XNOR Gate, Different Input 1. INTRODUCTION High speed, small area, low power and low cost are always expected by VLSI circuit engineers while designing for computing devices. Hand held devices such as mobile phones, laptops and phablets are becoming more and more popular everyday. Majority of the mobile users demand longer stand-by and talk time with higher operating frequencies. In CMOS, Deep Sub-Micron (beyond 65nm) transistors consume high static power. Practically, microprocessors or Digital Signal Processors (DSP's) have various complex signal processing modules such as audio and video compression, gaming and graphical modules to meet customer demands. It leads the processors or ICs to be of higher density. It is necessary to minimize thepower dissipation in portable, higher density and Deep Sub-Micron (DSM) based devices. Low power design has several merits such as less cooling cost and improved reliability. Also, it reduces the weight and makes the devices compact. It is important to provide high performance portable devices and it may not be compromised for low power dissipation. Normally, signal processing applications perform several tasks such as convolution, filtering, FFT, DCT of the signal, masking, filtering, stretching and image multiplication tasks are performed in image and video processing applications [1, 2]. Multiplication can be performed in different ways. Hardware complexity of the serial multipliers is lower than parallel multipliers. Researchers have analyzed and proposed several new structures for parallel multipliers because parallel multipliers are faster in nature. This is iterative and sequential multiplier. Repeated addition technique is used in this method. Multiplicand (M) bits are added with "N" times, where "N" is the size of multiplier. Fig. 1.1 shows the diagram of shift-and-add method. "N" bit multiplication is done with the help of Accumulator, ALU, registers for multiplicand and multiplier and control unit. The value of multiplicand is added and accumulated based on the LSBbit of multiplier. In every clock, multiplier bit is shifted right and the bit is tested. If the value is "1", multiplicand is added with accumulator and bits are shifted right else the accumulator value shifted right. This procedure repeats until all multiplier bits are tested. Finally, the result is in accumulator. The length of result is "2N" bits and this multiplier takes "N" cycle to complete the tasks. Conventional CISC machine uses this multiplier. This multiplier belongs to parallel multiplier category. In this multiplier, all partial product are generated in parallel. time to compute the final result is smaller than serial multiplier. This multiplier is used in high performance systems. Array of addersare used in each rows and columns. As word length increases, it is possible to extend the multiplier structure without affecting the existing structure. Pipelining is possible inarray multiplier whereas sequential and tree multipliers do not support pipeline. Sinceit has regular structure, place, and route, interconnection of cells are simpler than other multipliers. Moreover, this multiplier provides the simple VLSI circuit layout. 2. LOGIC GATE A logic gate is a position of controlled changes used to ascertain tasks utilizing Boolean rationale in advanced circuits. They are fundamentally completed electronically, however can similarly be built utilizing electromagnetic transfers, electronic diodes, liquids, optical or on the other hand even mechanical components. Cardinal attributes of the rationale entryways are:  The ability to interface with single or two information wires  The ability to interface with one yield wire  The ability to get an incentive from an associated input wire  The ability to convey an incentive to an associated yield wire  The capacity to figure right yield esteem, given current info value(s).