A 6 bit 800MHz TIADC based on Successive Approximation in 65nm Standard CMOS Process Arunkumar Salimath Chandrajit Debnath Sushanta K Mandal Kallol Chatterjee DA-IICT,Gandhinagar,India STMicroelectronics India Pvt. Ltd, arunk22.10@gmail.com Greater Noida, India Abstract Applications like Ultra-wideband radio, Optical Communication require sampling rates of at least 500MS/s with low resolution. The potential energy savings of successive approximation based time– interleaved A-D conversion architecture overrides traditional flash architecture. This paper presents a 6- bit 800 MS/s ADC in 65 nm STMicroelectronics standard CMOS process. The ADC uses 8-channel time interleaved SAR topology and achieves 36 dB SNR and 43 dB SFDR with 13.5 mW power consumption from 1.2 V supply. The resulting FOM is 0.3251 pJ/step. The timing mismatch among the channels is reduced by clock-edge reassignment technique. The high speed specification of the system requires the design of low offset comparator. Power consumption and jitter are reduced by using shift register based phase generator. 1. Introduction Digital receivers for high bit rate communications are constantly demanding high speed analog-to-digital communications with low power consumption being another concern. Applications like UWB and state-of - the-art disk-drive read channels require 5-6 bit resolution at conversion rates of 500 MS/s and beyond. Generally flash ADCs are perceived to be well suited for this kind of specification. But the low power requirement is the bottleneck. A flash ADC requires as many comparators in a conversion operation as the number of quantization levels and hence increasing area and power exponentially with resolution. Time interleaving is a promising technique being implemented actively over the years [1–2], [7]. The objective of TIADC design is to achieve the high conversion rate and low power consumption. This has motivated the design of successive approximation based ADC and has made the sampling rate of SAR ADCs competitive with flash ADCs. In this paper, a 6 bit successive approximation based time interleaved ADC is proposed. The architecture is fully differential thus significantly reducing clock feedthrough. In order to minimize the dynamic performance degradation due to the timing mismatch among the channels in the interleaving system, clock-edge reassignment technique is used [4]. The charge sharing DAC is implemented as a hybrid combination of resistors and capacitors to reduce the area. The SAR logic is also derived out of the channel phase generator thus synchronizing all the channels with a common reference in time domain. 2. Implementation Issues and Advantages In the design, the time interleaved unit ADC slices load the preceding stage of the system. In this configuration only two SAR stages are connected to the previous stage by sampling switches at a time. So, effective load of TIADC is same as two unit ADC load except for some additional load due to sampling switches of un-switched stages. As SAR ADCs do not require any opamp they are inherently low power consuming. Since the speed of operation is high the high speed comparator required in the unit ADC implementation has to be offset compensated so as to have low residual offset. The time interleaved systems suffer from periodic timing skew that produces modulation images at multiples of f s /M for ‘M’ periodic skews. As a result, for high speed applications the design of a low-jitter, non-overlapping multi-phase clock generator is critical. Another issue with the time-interleaved architecture is the channel offset and gain mismatches. For low resolution of six bits, the mismatch can be kept to a tolerable level with good component matching and careful design. The architecture is hardware efficient. With minimum amount of logic, the converter is steered to get digital output data. Also the analog circuitry is very simple: capacitors, switches and a comparator are sufficient. 2010 23rd International Conference on VLSI Design 1063-9667/10 $26.00 © 2010 IEEE DOI 10.1109/VLSI.Design.2010.55 312