Hindawi Publishing Corporation VLSI Design Volume 2007, Article ID 26454, 3 pages doi:10.1155/2007/26454 Editorial Networks-on-Chip: Emerging Research Topics and Novel Ideas Davide Bertozzi, 1 Shashi Kumar, 2 and Maurizio Palesi 3 1 Engineering Department, University of Ferrara, 44100 Ferrara, Italy 2 Department of Electronics and Computer Engineering, School of Engineering, J¨ onk¨ oping University, 55111 J¨ onk¨ oping, Sweden 3 Department of Information Engineering and Telecommunication, University of Catania, 95125 Catania, Italy Received 4 April 2007; Accepted 4 April 2007 Copyright © 2007 Davide Bertozzi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Networks-on-chip (NoCs) are being devoted intensive re- search efforts by R&D institutions all around the word, and it is our pleasure to host in this special issue the latest con- tributions on key design issues at different levels of abstrac- tion, namely, physical link design, architecture design and optimization, performance and power characterization, and design technology. Applying the networking concept to on- chip communication is part of the breakthrough solutions urged by the advances in silicon manufacturing technol- ogy (which keeps scaling well beyond 100 nm), by increased time-to-market pressures and by the growing computing re- quirements of current and future embedded applications. In fact, scalable computation horsepower has been traditionally provided through an increase of clock frequency of mono- lithic processor cores at each technology node. This trend is, however, running into the barriers of nanoscale technolo- gies, such as heating levels beyond the capability of state-of- the-art packaging and cooling technologies, limited scaling of memory access times and the von Neumann bottleneck. These limitations are being increasingly overcome by break- ing up functions into concurrent tasks, assigning them to parallel computational units and operating them at a lower frequency than monolithic cores. This approach paves the way for energy-efficient massively parallel chip-level compu- tation architectures, which are at the core of multiprocessor system-on-chip (MPSoC) technology. This trend has profound implications on the commu- nication architecture as well, since the communication re- quirements of an increasing number of processor cores have to be accommodated by the system interconnect. In con- trast, state-of-the-art interconnect fabrics will soon incur severe scalability limitations. The International Technology Roadmap for Semiconductors foresees that they will rep- resent the limiting factor for performance and power con- sumption in next generation SoCs. In the last few years, a number of advances in on-chip interconnect architectures have tried to relieve the limitations of the communication sub-system. First, more parallel topologies have been pro- posed to increase the amount of delivered bandwidth, such as partial or full crossbars. However, scalability limitations of crossbar-based interconnection fabrics are well known, and they will not be a long-term solution. Second, new communication protocols have been developed, aiming at a more effective exploitation of the available bandwidth. AMBA 3.0 AXI and the open-core protocol (OCP) are ex- amples thereof. Interestingly, these latest protocols provide support for point-to-point communication only (e.g., an IP core with a bus or directly with another IP core) and do not provide any specification on the interconnect fabric, which can (almost) freely evolve in the direction of a higher com- munication parallelism. In a short span of seven years, networks-on-chip (NoCs) have been recognized as the most important alternative for the design of modular and scalable communication archi- tectures, providing inherent support to the integration of heterogeneous cores through standard socket interfaces. Not only NoCs relieve system-level integration issues, but are also suitable to deal with the challenges of nanoscale technol- ogy. The degradation of the RC propagation delay of signals across global wires is in fact making multiclock cycle signal propagation come true. At the same time, design predictabil- ity of global chip-wide structures (like some state-of-the-art system interconnects) is increasingly jeopardized. Through an aggressive path segmentation, NoCs loosen the delay bot- tleneck of on-chip interconnects and improve design pre- dictability. Unfortunately, area and power overheads incurred by current NoC prototypes remain still significant in spite of the performance benefits, calling for further research ef- forts to make this solution more mature and viable from an