Drive current and threshold voltage control in vertical InAs wrap-gate transistors C. Rehnstedt, C. Thelander, L.E. Fro ¨berg, B.J. Ohlsson, L. Samuelson and L.-E. Wernersson Results on fabrication and DC-characterisation of vertical InAs nano- wire wrap-gate field-effect transistor arrays with a gate length of 50 nm are presented. Each nanowire array was processed into a transis- tor with a systematic variation in a number of wires and wire diameter over the sample. Extensive studies have been performed on the influ- ence of wire number and diameter on the transistor characteristics due to a high device yield (84%). In particular it is shown that the threshold voltage depends on the wire diameter, with a change in the order of 5 mV/nm. These results show the possibility of changing the transistor characteristics on the sample by altering the wire dimen- sions, still using only one patterning and growth sequence. Introduction: Many III–V materials, including InAs, have advan- tageous material properties, such as low contact resistance, high electron mobility and high saturation velocities, which may enable high-speed and low-power devices and applications [1]. From a design perspective, nanowire (NW) wrap-gate transistors offer improved electrostatic control and higher flexibility in heterostructure design. Long-channel transistors have already been shown to exhibit good device characteristics [2], but there is a need to further develop the processing and to reduce the gate- length. In this Letter, we compare data for roughly 100 metal–insula- tor – semiconductor field-effect transistors (MISFETs) with 50 nm gate-length fabricated in one batch and show that key parameters such as drive current, transconductance and threshold voltage can be changed systematically by controlling the diameter of the nanowires and the number of wires in the matrices. Nanowire growth: InAs NWs (n-type, 2–5  10 17 cm 23 ) were grown on an InAs (111)B substrate (n-type, 3  10 18 cm 23 ) using chemical beam epitaxy. Au seed particles, defined in matrix patterns on the sub- strate using electron-beam lithography and a lift-off process, were used for the NW growth [3]. The wires were grown at 4308C with trimethyl- indium and tertiarybutylarsine as precursors. The wire lengths ranged from 0.4 to 1.2 mm depending mainly on the diameter; thinner NWs are observed to grow faster. The NW diameter and the matrix size were varied systematically among the transistors. Three different wire diameters were defined (40, 60 and 75 nm) in five different matrix sizes (7, 19, 37, 61 and 91 NWs). Each combination of diameter and matrix size was repeated eight times on the substrate, forming a total of 120 matrices, one for each transistor array. These arrays covered a total wafer area of 20 mm 2 . Fig. 1 I D – V DS characteristics of typical device with 91 nanowires of 60 nm diameter Inset: schematic cross-section of fabricated structure Processing: Using atomic layer deposition, 10 nm of HfO 2 was depos- ited at 2508C as gate dielectric. A 50 nm-thick chromium gate layer was then evaporated to form the gate layer, and gate structures were defined by optical lithography. The HfO 2 was removed from the top of the NWs in buffered HF using a photoresist to protect the base. A 140 nm-thick layer of SiN x was deposited by plasma enhanced chemical vapour deposition at 3508C in order to isolate the drain from the gate. The SiN x at the top of the NWs was then etched using CF 4 reactive ion etching with a photoresist as mask, forming a gate-to-drain separation between 100 and 300 nm, the exact value depending on the nanowire length in each array. The uncovered part of the NWs was sulphur passi- vated, and finally a Ti/Au contact was formed by evaporation, optical lithography, and etching (Fig. 1 inset). It is important to note that all these process steps are inherently scalable. Using this process scheme, NW transistors with different diameters and matrix dimensions could be processed simultaneously, minimising process related variations. Fig. 2 Current normalised by gate width (defined as total NW circumference within array) and current densities against nanowire matrix size y-axes are scaled so that data fit both axes Characterisation: Electrical DC characterisation of the MISFETs was performed using the InAs substrate as the source. The measurements showed a high yield (84%) of functional transistor arrays. The I D – V DS characteristics for a typical device are shown in Fig. 1. The currents in all Figures have been normalised by the gate width, defined as the total NW circumference within the array, in order to facilitate compari- son with other transistor geometries [4]. No current saturation was observed, which is due to large series resistance on the drain side, short channel effects and impact ionisation. The devices show reprodu- cible characteristics up to 3 V with a breakdown voltage around 3.5 V. The drive current and current density were further analysed for a fixed gate overdrive, V GS ¼ V T þ 2/3  V DS , against matrix size (see Fig. 2). The values were determined for V DS ¼ 0.5 V as the devices are of relevance to low-power applications. Since the drive current and the current density have been normalised to the number of wires they should not depend on the matrix size. However, a small dependence was still observed, which is believed to be related to an increased percen- tage of functioning wires, and a reduced series resistance, in the larger matrices. The threshold voltage, V T , is extracted by a linear fit at the maximum transconductance; the result is shown in Fig. 3. The extracted values are in the range 20.8 to 21.1 V at V DS ¼ 0.5 V, shifting to more negative values as the diameter increases. To describe the threshold voltage shift, we use a MISFET model, V T ¼ V fb  qN d r 2 41 InAs 1 0  qN d r 2 21 HfO2 1 0 ln r þ t r   where 1 InAs and 1 HfO 2 are the relative permittivities of InAs and HfO 2 , respectively, N d is the channel doping, t the thickness of the HfO 2 gate dielectric and r the NW radius. Using parameters extracted from reference structures, 1 InAs ¼ 15.2, 1 HfO 2 ¼ 15.0, N d ¼ 4  10 17 cm 23 , t ¼ 10 nm, the model implies a diameter-dependent threshold voltage shift of 5 mV/nm for a starting diameter of 60 nm. This is indicated by a line in Fig. 3. The fluctuation in V T is believed to be caused by growth related length variations which affect the total NW resistance, as well as diameter variations (approximately +5 nm on the diameter) within the arrays due to proximity effects in the electron-beam definition of the seed particles. A flat-band voltage of 20.75 V is deduced, which originates from the difference between the chromium work function and the InAs affinity, and from charges in the HfO 2 and SiN x layers. From the transfer characteristics, we also deduce a peak value for the normal- ised transconductance of 235 mS/mm at V GS ¼ V T þ 0.5 V and V DS ¼ 1 V. These extrinsic values are highly affected by the series resistances in the source and drain regions of the wires. The DIBL is typically 150 mV/V. We also measured a subthreshold slope of 750 mV/ decade at V DS ¼ 0.5 V for NW transistors with 60 nm diameter, and a maximum hysteresis of 160 mV in the sub-threshold region. This ELECTRONICS LETTERS 31st January 2008 Vol. 44 No. 3