> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Fig. 1. General model for NVM with 6T cell as SRAM core. Abstract—Energy consumption is a major concern in nanoscale CMOS ICs; the power-off operational mode and low voltage circuits have been proposed to alleviate energy dissipation. Static Random Access Memories (SRAMs) are widely used in today’s chips; non-volatile SRAMs (NVSRAMs) have been proposed to preserve data, while providing fast power-on/off speeds. Non-volatile operation is usually accomplished by the use of a Resistive RAM circuit (hence referred to as RRAM); the utilization of a RRAM with an SRAMs not only enables chips to achieve low energy consumption for non-volatile operation, but it also permits to restore data when a restore on power-up is performed (this operation is also commonly referred to as “Instant-on”). This paper presents a novel NVSRAM circuit for “Instant-on” operation and evaluates its performance at nanometric feature sizes. The proposed memory cell consists of a SRAM core (in this case, a 6T cell) and an Oxide Resistive RRAM circuit (1T1R), thus making a 7T1R scheme. The proposed cell offers better non-volatile performance (in terms of operations such as “Store”, “Power-down” and “Restore”) when compared with existing non-volatile cells. The scenario of multiple-context configuration is also analyzed. Figures of merit such as energy, operational delay and area are also substantially improved, making the proposed design a better scheme for “Instant-on” operation. Index Terms—Static Random Access Memory (SRAM), HSPICE, Resistive RAM, Non-volatile Memory, NVSRAM, Leakage Reduction. I. INTRODUCTION ecent advances in memory technology have made possible new modes of operation for nanoscale Integrated Circuits (ICs). For example, Field Programmable Gate Arrays (FPGAs) have mostly utilized Static Random Access Memories (SRAMs) as programming technology [1] [2] [3]. However with the reductions in supply voltage and feature size, the leakage current of a SRAM has considerably increased, thus becoming a major source of energy consumption when the IC is in standby mode [1]. However, SRAMs are volatile, so, non-volatile storage is required for power-down operation. A non-volatile SRAM (NVSRAM) W. Wei and F. Lombardi are with the Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA; email: lombardi@ece.neu.edu; K. Namba is with the Graduate School of Advanced Integration Science, Chiba University, Chiba, JAPAN, email: namba@ieee.org; Jie Han is with the ECE Dept, University of Alberta, Edmonton, Canada, email: jhan8@ualberta.ca Copyright (c) 2014 IEEE. Personal use of this material is permitted. However, permission to use this material for any other other purposes must be obtained from the IEEE by sending a request to pubs-permissions@ieee.org. can combine the benefit of a simple access and a nearly unlimited “Store” capability of a SRAM with a non-volatile element, such as an EEPROM (electrically erasable programmable ROM). In the past non-volatile RAMs had the disadvantages of low density (at most 4 Kbit) and significantly lower speed than a volatile SRAM [4]. Through the years, increased density (64 Kbit) and faster access (30ns for military standard ICs) have been reported for NVSRAMs [4]. The NVSRAM is normally accessed like any static RAM and a “Restore” signal is utilized to clear the volatile data held in the SRAM and replace it with the data held in the non-volatile storage when a “Restore” on “Power-up” is performed. This operation is also commonly referred to as “Instant-on” [1] [3]. The continued growth of semiconductor non-volatile memories will likely rely on advances in both electronic materials and device structures. Extensive efforts have been devoted to address these two complementary issues. Resistance switching is the basic physical phenomenon in the operation of a Resistive Random Access Memory (RRAM); this phenomenon has been studied for more than 40 years [5]. In addition to its non-volatile operation, one of the most evident advantages of a RRAM is its compatibility with CMOS processes, such that the current infrastructure can be readily applied to its fabrication/manufacturing. Furthermore, the scaling merit of a RRAM permits to operate at low energy consumption, making it a very competitive technology for large storage at low costs. In the past decade, several novel techniques have been proposed for implementing NVSRAMs, such as ferroelectric capacitors [6], phase change [7], non-polar Resistive Switching Devices (RSDs) [8], nanocrystal PMOS flash [9], Spin-Transfer-Torque MTJs (STT-MTJs) [10] and the memristor [11]. The Oxide Resistive RAM (OxRRAM) represents yet another attractive technology for implementing a RRAM. OxRRAMs are compatible with a CMOS process flow, while offering advantages, such as high scalability and good operating speeds [5]. Moreover, storage of multiple bits on a single memory cell (i.e. on a non binary basis) has also been Design of a Non-Volatile 7T1R SRAM Cell for Instant-on Operation Wei Wei, Student Member, Kazuteru Namba, Member, Jie Han, Member and Fabrizio Lombardi, Fellow R