A low-cost built-in error correction circuit design for STT-MRAM reliability improvement Wang Kang a,c , WeiSheng Zhao a,b,⇑ , Zhaohao Wang a,b , Yue Zhang a,b , Jacques-Olivier Klein a,b , Youguang Zhang c , Claude Chappert a,b , Dafiné Ravelosona a,b a IEF, Univ. Paris-Sud 11, Orsay 91405, France b UMR8622, CNRS, Orsay 91405, France c Electrical Engineering Department, Beihang University, Beijing 100191, China article info Article history: Received 22 May 2013 Received in revised form 26 June 2013 Accepted 10 July 2013 abstract Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) possesses various merits, such as non-volatility, low power and high speed. It has been considered as a promising non-volatile memory candidate used universally in logic computing, cache and storage applications. However it suffers from serious reliability issues compared with conventional schemes, especially in deep submicron technolo- gies. This paper proposes a low-cost built-in error correction circuit to improve STT-MRAM reliability. Its straightforward ‘‘XOR’’ encoder and one-step majority-voting decoder provide much lower area and higher speed compared with conventional ECCs, and its modular codec structure allows adaptive error correction capability according to the system requirement. Simulation based on a compact STT model and STMicroelectronics 40 nm technology node was carried out to confirm its effectiveness. Ó 2013 Elsevier Ltd. All rights reserved. 1. Introduction Spin Transfer Torque Magnetic Random Access Memory (STT- MRAM) promises various merits such as non-volatility, low power, infinite endurance and high speed [1–3]. It has been expected as an emerging ‘‘universal memory’’ for logic computing, cache and stor- age applications, and considered to be able to replace all other types of memories [4–6]. These advantageous features attract much attention of R&D, a number of pre-industrial prototypes have been demonstrated since 2005 [4,5] and one expects to widely commercialize it in the next few years. However, STT-MRAM suf- fers from serious reliability challenges due to its intrinsic stochas- tic switching mechanism and the process voltage temperature (PVT) variations etc. [7–9], especially as technology scales. Fig. 1 shows its raw bit error rate (BER) performance under several typ- ical technology nodes. Though many circuit design techniques and strategies, such as self-enable switching, advanced thin film tech- niques and sensing circuits [9–11], have been proposed recently to improve its reliability, the final BER is still high (>10 À5 ) and insufficient for reliable usages. Therefore, STT-MRAM needs error correction code or circuit (ECC) to guarantee its reliability as con- ventional memories (e.g. SRAM and Flash). Triple Modular Redun- dancy Code (TMRC) and Hamming code are two popular error correction schemes used widely in logic computing and cache [12,13]. However, Hamming provides very limited error correction capability t (t= 1), which cannot address the particularly high BER of STT-MRAM, while TMRC leads to large area redundancy and high power. Other multi-bits error correction ECCs, such as Bose–Chau- dhuri–Hocquenghem (BCH) code and Low-Density Parity-Check (LDPC) code [12], are usually used in mass storage applications and they are rarely employed for logic computing and cache due to their high complexities and decoding latencies. Thereby, there are no efficient ECC solutions that can be employed straightfor- wardly for STT-MRAM to be used as a universal memory. This pa- per then proposes a low-cost error correction circuit derived from Orthogonal Latin Square Code (OLSC) [14,15], which is imple- mented in a built-in form and can be employed as an inner code for STT-MRAM. 2. STT-MRAM backgrounds STT-MRAM is based on the magnetization programming of the magnetic tunnel junction (MTJ) (see Fig. 2 (a)), which is mainly composed of one oxide barrier layer (e.g. MgO) sandwiched be- tween two ferromagnetic (FM) layers (e.g. CoFeB). A MTJ presents the two resistance values (R P or R AP ) depending on the relative magnetization orientations of the two FM layers (parallel (P) or anti-parallel (AP)). The resistance difference of these two states is characterized by the Tunnel Magneto-Resistance (TMR) ratio [1,2]. Only a low bi-directional spin polarized current I write larger than a threshold value I C0 (<100 lA@40 nm) can switch the MTJ (see Fig. 2 (b)) and a directional read current I read less than I C0 0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2013.07.036 ⇑ Corresponding author at: IEF, Univ. Paris-Sud 11, Orsay 91405, France. Tel.: +33 (16915) 6292; fax: +33 (16915) 4000. E-mail address: weisheng.zhao@u-psud.fr (W. Zhao). Microelectronics Reliability 53 (2013) 1224–1229 Contents lists available at SciVerse ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel