IEEE SENSORS JOURNAL, VOL. 2, NO. 4, AUGUST 2002 279 Ion-Sensitive Field-Effect Transistors in Standard CMOS Fabricated by Post Processing C. G. Jakobson, U. Dinnar, M. Feinsod, and Y. Nemirovsky, Fellow, IEEE Abstract—Highly integrated ion-sensitive field-effect transistor (ISFET) microsystems require the monolithic implementation of ISFETs, CMOS electronics, and additional sensors on the same chip. This paper presents new ISFETs in standard CMOS, fab- ricated by post-processing of a standard CMOS VLSI chip. Un- like CMOS compatible ISFETs fabricated in a dedicated process, the new sensors are directly combined with state-of-the-art CMOS electronics and are subject to continuous technology upgrading. The ISFETs presented include an intermediate gate formed by one or more conducting layers placed between the gate oxide and the sensing layer. The combination of the highly isolating gate oxide of the MOS with a leaky or conducting sensing layer allows the use of low temperature materials that do not damage the CMOS chip. The operation of ISFETs with an intermediate gate and sensing layers fabricated at low temperature is modeled. ISFETs with a linear pH response and drift as low as 0.3 mV/h are reported. Index Terms—CMOS, ISFET, microsystem, MOSIS, pH, stan- dard. I. INTRODUCTION O NE OF today’s challenges is the integration of ion–sensi- tive field–effect transistors (ISFETs) in chemical and bio- chemical microsystems for applications such as in-vivo analysis, micro total analysis systems ( TAS), lab-on-a-chip, or elec- tronic tongues. These microsystems usually require the mono- lithic combination of ISFETs and MOSFETs on the same chip. In previous works, the monolithic fabrication of ISFETs and MOSFETs has been achieved by specially dedicated processes or introducing extra steps and shortcuts to an existing process [1]–[6]. On the other hand, ISFETs fabricated in an unmodified CMOS process show large threshold voltages and use oxynitride as the pH-sensitive layer [7]. This paper presents new ISFETs in standard CMOS, which are compatible with standard CMOS processes and are fab- ricated by post-processing of a standard CMOS VLSI chip. The ISFETs studied can be readily integrated with CMOS electronics, and can be either n-channel or p-channel devices. Several designs and post-processes are studied, modeled, Manuscript received April 11, 2001; revised April 25, 2002. This work was supported by the Women Division/ATS MEP XXV Project. The work of C. G. Jakobson was supported by the Israeli Ministry of Science under a Eshkol Scholarship. The associate editor coordinating the review of this paper and approving it for publication was Prof. Julian W. Gardner. C. G. Jakobson and U. Dinnar are with the Department of Biomedical Engineering, Technion—Israel Institute of Technology, Haifa, Israel (e-mail: claudio@tx.technion.ac.il). M. Feinsod is with the Department of Medicine, Technion—Israel Institute of Technology, Haifa, Israel. Y. Nemirovsky is with the Department of Electrical Engineering, Tech- nion—Israel Institute of Technology, Haifa, Israel. Digital Object Identifier 10.1109/JSEN.2002.802237 Fig. 1. Cross section of the standard CMOS ISFET. fabricated, and tested. Some of the processes presented lead to successful sensitive, linear, and low drift devices. The ISFETs presented provide several important advan- tages: 1) The ability to be integrated with the state-of-the-art CMOS electronics, as well as other CMOS compatible sensors for multi-modal applications; 2) unlike dedicated process ISFETs, the new sensors are subject to continuous technology upgrading; and 3) wide availability and low cost. The basic structure that serves as the basis for the ISFET is fabricated in a standard CMOS chip through MOSIS [8]. An ex- posed aluminum layer is found at the top of the structure to allow the opening of the glass. Several post processes are performed on this structure in order to make it ion sensitive, including evap- oration of aluminum oxide, tantalum oxide, platinum, titanium, and wet etching of aluminum. The fabrication procedure leaves an intermediate gate placed between the gate oxide and the sensing layer. The intermediate gate is formed by one or more conducting layers that may form part of the standard CMOS process, like aluminum and polysil- icon, or of the post-processing, like titanium and platinum. A new model is presented in this paper that describes the opera- tion of ISFETs with an intermediate gate. The model considers leaky or conducting sensing layers that can be fabricated in a low temperature process and shows that the excellent isolating properties of the CMOS gate oxide are enough to guarantee the potentiometric operation and the pH sensitivity of the ISFET. This study shows that the main difficulty in fabricating the ISFET by direct evaporation of the sensing layer on the basic structure is the corrosion of the aluminum layer [9]. Devices fabricated in this way can be only used for low-resolution ap- plications. The following solutions for the corrosion problem are studied and successfully implemented, which provide good quality devices showing high resolution: 1) protection of the alu- minum layer from corrosion using a titanium–platinum double- metal layer and 2) etching of the aluminum layer, using it as a sacrificial. 1530-437X/02$17.00 © 2002 IEEE