Low-frequency noise in bare SOI wafers: Experiments and model L. Pirro ⇑ , I. Ionica, S. Cristoloveanu, G. Ghibaudo Univ. Grenoble Alpes, IMEP-LAHC, F-38000 Grenoble, France CNRS, IMEP-LAHC, F-38000 Grenoble, France article info Article history: Available online xxxx The review of this paper was arranged by Jurriaan Schmitz Keywords: SOI Pseudo-MOSFET Interface trap density Low-frequency noise abstract Low-frequency noise (LFN) measurements are largely used for interface quality characterization in MOSFETs. In this work, a detailed investigation of LFN technique applied to pseudo-MOSFETs in bare silicon-on-insulator (SOI) substrates is provided. A physical model capable to describe the experimental results is proposed and validated using different die areas and inter-probe distances. The effective silicon area contributing to the noise signal, the impact of defects induced by probes and the possibility to extract interface trap density are addressed. Ó 2016 Published by Elsevier Ltd. 1. Introduction The interest of SOI substrates for microelectronics does not need justification anymore [1–3]. High performance SOI devices are possible only using premium quality wafers with high carrier mobility (l) in the top silicon film and low traps density (D it ) at the interface between the top silicon film and the buried oxide (BOX). In this context, electrical characterization techniques of bare SOI samples (before CMOS integration flow) are needed to determine l and D it values. These parameters are usually mea- sured with the pseudo-MOSFET (W-MOSFET) configuration. Thanks to the possibility to directly investigate the properties of both types of carriers (i.e., electrons and holes) with the same structure, the W-MOSFET has largely proved its interest ever since its discovery [4–7]. To perform electrical characterization, the SOI structure is placed on a metal chuck. A gate bias (V G ) applied on the substrate induces free electrons (V G > 0) or holes (V G < 0) at the interface between the top silicon film and the BOX. Two adjustable- pressure probes are placed on the silicon film surface and used to access the conduction channel (inset Fig. 1a). Fig. 1a shows a typical transfer characteristic I D (V G ), drain current as a function of gate bias. The effective mobility can be extracted from I D (V G ) curves with the Y-function or by performing split-CV measurements [7–9]. The interface state density is normally evaluated from the subthreshold swing (S) of log I D (V G ) curves, given by [10]: S ¼ 2:3  k  T q  1 þ C Si þ q  D it C OX   ð1Þ where k is the Boltzmann constant, T the temperature and q the electron charge. C Si and C OX are the capacitances of the top silicon film and BOX, defined as C Si = e Si /t Si and C OX = e OX /t OX , with t Si and t OX being the corresponding thicknesses; e Si is the silicon dielectric constant and e OX the one associated to SiO 2 . Using Eq. (1), the slope of the linear fit performed in the sub- threshold region (dashed line in Fig. 1a) yields the interface trap density: D it  10 12 cm 2 eV 1 . Nevertheless, the thinning of the top silicon film and the consequent increase of C Si affect the reso- lution of D it extraction for ultrathin Si (C Si  q  D it ). This is why new characterization techniques to monitor the interface quality are required to overcome this limit. The C-V conductance method is not adapted for D it evaluation [11]. Another approach proposed by Daanoune et al. [12] utilizes the photo-conductance technique in pseudo-MOSFET setup to extract D it . However, the use of exter- nal laser source makes the method tedious. Low-Frequency Noise (LFN) measurements are largely used for D it investigation in plain MOSFETs [13–15]. Thus, this technique is a good candidate for interface characterization of SOI substrates. Kushner et al. [16,17] proved the possibility to characterize SOI wafers with LFN, using evaporated contacts. However, the presence of Schottky barriers makes the extraction procedure complicated. Diab et al. [18] demonstrated the feasibility of noise measurements directly in W-MOSFET configuration with pressure probes. http://dx.doi.org/10.1016/j.sse.2016.07.012 0038-1101/Ó 2016 Published by Elsevier Ltd. ⇑ Corresponding author at: Univ. Grenoble Alpes, IMEP-LAHC, F-38000 Grenoble, France. E-mail address: pirrol@minatec.inpg.fr (L. Pirro). Solid-State Electronics xxx (2016) xxx–xxx Contents lists available at ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse Please cite this article in press as: Pirro L et al. Low-frequency noise in bare SOI wafers: Experiments and model. Solid State Electron (2016), http://dx.doi. org/10.1016/j.sse.2016.07.012