Effect of Selective Oxidation Conditions on Defect Generation in Gate Oxide Heung-Jae CHO,  Kwan-Yong LIM, Se-Aug JANG, Jung-Ho LEE, y Jae-Geun OH, Yong Soo KIM, Hong-Seon YANG and Hyun-Chul SOHN Memory R&D Division, Hynix Semiconductor Inc., Ichon P.O. Box 1010, Ichon-si, Kyoungki-do 467-701, Korea (Received September 18, 2003; accepted January 8, 2004; published April 27, 2004) We studied the effect of selective oxidation conditions on gate oxide characteristics. Selective oxidation in hydrogen-rich wet ambient at 850  C–950  C was found to generate defects both at the SiO 2 /Si interface and in oxide bulk, resulting in a higher stress-induced leakage current. The degradation of the device can be explained by the incorporation of hydrogen into the gate oxide during a high-temperature selective oxidation process. The plasma reoxidation process induced fewer defects due to radical oxidation at low temperature. [DOI: 10.1143/JJAP.43.1825] KEYWORDS: selective oxidation, plasma reoxidation, W/poly-Si, defect generation 1. Introduction With the shrinkage of memory devices below sub-100 nm technology, the gate electrode with low resistivity is more required to improve device speed. Tungsten/polysilicon (W/poly-Si) has been widely studied due to its low resistivity. One of the problems in the W/poly-Si gate is the oxidation of W during conventional gate reoxidation in O 2 ambient after gate patterning. A selective oxidation (SO) process in H 2 -rich H 2 O ambient is considered to be the solution, where Si is selectively oxidized without the oxidation of W. 1) The incorporation of hydrogen into the device, however, has a strong effect on the electrical characteristics of the device. Annealing in hydrogen ambient is used for the passivation of silicon dangling bonds in Si- based devices. 2,3) The hydrogen introduced for the passiva- tion of these defects is known to create defects in gate oxide during a device operation. The hydrogen released into the oxide by radiation or electrical stress generates interface states and subsequently degrades the electrical character- istics of the oxide such as enhanced hot carrier degradation and negative bias temperature instability. 4,5) High-temper- ature annealing in N 2 /H 2 forming gas is also reported to generate mobile hydrogenous positive ions in the oxide which can be electrically driven across the oxide. 6–8) It is therefore expected that the gate oxide reliability in the W/ poly-Si/SiO 2 is also degraded by the SO process. The effect of the SO process in H 2 -containing ambient has, however, not reported in detail. In this paper, we report the effect of the SO process on the degradation of gate oxide in terms of stress-induced leakage current (SILC), oxide trap density, and interface state density (D it ). 2. Experimental For electrical measurements, the W film was not em- ployed on the poly-Si in order to exclude issues of W contamination and W oxidation during gate reoxidation. n+Poly-Si (1500  A)/SiO 2 (55  A)/Si nMOS capacitors with shallow trench isolation were fabricated on p-type (100) Si substrates (8-inch dia.). After gate patterning, gate reoxida- tion was carried out in H 2 -rich H 2 O ambient at high temperatures from 850  C to 950  C, where the reoxidation time was adjusted for a constant oxide thickness. Some samples were reoxidized at 850  C in a furnace (FO) or rapid thermal process (RTP) system (RTO) in O 2 ambient for comparison. In addition, plasma gate reoxidation, which can oxidize Si selectively, was performed in Ar/H 2 /O 2 plasma ambient at 250  C. Post-N 2 -annealing processes were then carried out in a furnace (150 min at 710  C) and in an RTP system (10 s at 1000  C), followed by H 2 /N 2 forming gas annealing. Electrical properties such as the current density–voltage (J -V ) and SILC were measured using an HP4156A on 100  100 mm 2 MOS capacitors. Interface traps at SiO 2 /Si- substrate and the charge state in the gate oxide of the MOS capacitors were characterized by the capacitance-voltage (C-V ) and the conductance method via small ac signal admittance measurements in the frequency range of 1 kHz to 1 MHz using an HP4284A LCR meter. The cross-sectional profile of the W/poly-Si gate was examined by high- resolution transmission electron microscopy (HRTEM). 3. Results and Discussion Shown in Fig. 1 are the J -V curves of several MOS capacitors measured before and after a stress of 1 C/cm 2 . -1 -2 -3 -4 -5 -6 10 -9 10 -7 10 -5 10 -3 Fresh FO, w/ PA SO, w/ PA SO, w/o PA After -1C/cm 2 Gate Current (-A/cm 2 ) Gate Voltage (V) 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 -1 10 0 10 1 10 2 FO, w/ PA SO, w/ PA SO, w/o PA @ -10mA/cm 2 Normalized Leakage Increase: (J-J 0 )/J 0 Injected Charge [-C/cm 2 ] Fig. 1. J-V curves of various MOS capacitors before and after electrical stress of 1 C/cm 2 . The inset is the normalized gate leakage current versus injected charge plot, where the sensing voltage was 4:9 V because the maximum stress-induced leakage current is monitored at the voltage. (J 0 : gate current before stress, J: gate current monitored after charge injection).  E-mail address: heungjae.cho@hynix.com y Present Address: Department of Chemical Engineering, Hanyang Uni- versity, Ansan, Kyoungki-do 425-791, Korea. Japanese Journal of Applied Physics Vol. 43, No. 4B, 2004, pp. 1825–1828 #2004 The Japan Society of Applied Physics 1825