Design of Reconfigurable Logic Controllers from Petri Netbased specifications Marian Adamski, Marek Węgrzyn ! "! #$!$!% & ’()*+ (),-./)-)-)0 Abstract: The paper promotes to construct a synthesizable VHDL model from a graphical representation of Petri Net. The VHDL code provides a clear semantics of graphically designed reconfigurable logic controller and serves as reference model for eventual further optimization efforts. It is considered that automatically generated array structure of logic controller is optimized for synthesis by professional tools. The most useful aspect for presented purposes is the ability to execute a VHDL behavioral specification closely related with array"based implementation. Even if the final implementation is not optimized during the logic synthesis process, it is compact, easy to modify and efficient. 12 Reconfigurable Logic Controller, Petri Net, FPGA, VHDL, Rapid prototyping, Logic Synthesis. 1. INTRODUCTION Petri nets (David and Alla, 1992; Girault and Valk, 1992) provide a mechanism, which is suited to representing sequential order, concurrency and hierarchy in complex discrete processes. The Petri nets can be used both as specification and synthesis models for Reconfigurable Logic Controllers, nested inside modern, reactive microsystems (Yakovlev et al., 2000; Adamski et al., 2005). The main aim of this paper is to demonstrate a practical, methodology of mapping Concurrent Digital Systems into reconfigurable FPGAs (Field Programmable Gate Arrays) (Adamski, 1991; Węgrzyn et al., 1996). The Petri net serves as a formal model, both for rapid prototyping as well as for optimized synthesis, performed by means of commercial tools, approved by electronic industry. The designer can take an advantage of Hardware Design Languages like VHDL or Verilog by using them at different levels of abstractions. To avoid the complicated model transformations the behavioral description is given in synthesizable HDL, where the Petri net, VHDL model and the final circuit are asserted in terms of formal logic statements, described as Decision Rules. The presented approach makes possible to produce economical array"based implementations of intelligent reconfigurable logic controllers for modern industrial systems. This paper provide an overview of the original formal design methodology for reconfigurable controllers for industrial control systems. The hardware implementation of Petri net is particularly recommended for high"speed, parallel, dependable controllers, interacting with several concurrent discrete"event processes. The unique hardware description language is using during the whole development procedure, including the logic design. Other advantages of FPGA"based implementation of controllers are improved performance, reusability, fast prototyping, and testability. The reconfigurable controller fully implements a structure of discrete algorithm and its desired properties. 2. RECONFIGURABLE DIGITAL EMBEDDED SYSTEMS Fig. 1 depicts the controlled part of a designed simple reactive system. The controlled system consists of three tankers , and that can go on the left () or right () side. The tankers start movement together from the points *3)))*# after signal 4. They go concurrently to the points 5365#) Because, the tanker has the highest priority, it comes back first to the point *3. After that tanker goes back to its initial position *$. Tanker has the lowest priority. Fig. 1. Discrete embedded system Reconfigurable Controllers are flexible dedicated devices, implemented in array"based logic. Outputs of the controller represent a set of control signals for driving the actuators (738368#). They depend on the signals from sensors *36*# and internal signals 9 from distributed state register (Mandado et al., 1996; Milik and Hrynkiewicz, 2001).