AN AUTGMATED DATA PATH SYNTHESIZER FOR A CANONIC STRUCTURE, IMPLEMENTABLE XN VLSI Kumar Ramayya. Anshul Kumar, Surendra Prasad Department of Electrical Engineering, Indian Institute of TechnoIogy, Delhi, India. ABSTRACT Digital design complexity and the advent of VLSI has increased the need for design automation techniques. This paper discusses the mapping of the data part specified at a behavioural level onto a canonical structure, Data Node Array (DNA). The DNA is a paramctrired, reguIar sttuc- turc which is capable of realizing an arbi- trary, complex and parallel behavioural descriptions. The problem of transforming the input description to a Iayoot is form- ulated using a graph modeI and an algorithm for the data synthesis is given. An example illustrates the aIgorithm and the caprbili- ties of the structure. I INTRODUCTION Need for design automation has gained fu,rther impetus with the coming of VLSI. The possibility of realizing complex digi- tal systems on a single chip, is a fast becoming reality. It is now essential to think of the overall design, from a high level description of the system right down to the level of layout. Silicon compilation as it is fancifully called attempts to crc- ate an environment where the above said can be achieved. The design description at a behavioural level is transformed successi- vely into various levels of representation and ultimately refined to produce a layout. At each stage of representation more and more detai1 is added after exploring vari- ous design styles and also ensuring the correctness of the transformations made. Traditionally, any digital system can be broken up into a data part which repre- sents the data carriers and operators, and the control part which directs the flow >f information in the data part. This division is essen.iaI as the techniques employed in the realization of the two parts are quite distinct. Intensive work is ongoing at var- ious universities for autosaticaliy synthe- siring the data a?c? control parts Carnt- qie Mellon University Design Automatiin System’ (CMUDA) and MacPitts c>mpilsr at Massachusetts Institute of Tec.‘inology are two significant efforts towards a conplate system. One such total environment is also being envisaged by the Computer Aided Des- ign (CAD) group at Indian Institute of Technology, Delhi, Indiaq. In the CMVDb2, a behaviouraf descrip- is first transformed to an internal data flow representation, and later to a logic structure, after examining various design styles. The layout of this logic structure is not considered during the proccsr of sy-. thesis but performed later by usual place- ment and routing techniques. In the Mac- Pitts system’ a Lisp-like description is mapped onto a target architecture. However, only systems that have limited parallelism and tit into the framework of microprogram sequence data path operations can be synth- esized by MacPitts compiter. The design automation system at IIT, Delhi can synthesize :omplex digital sye- terns that are asynchronous, fully parallel or pipeIined. The designer specifies his design in Rachna, a behavioural and hisrar- chical hardware desc-iption language Sd6 . The translator convezts the description in- to an internal description in the form of expression trees, a symbol table and R-Net 4 (a modified form of Petri Net), which abs- tracts both the data and control specifica- tions in th* Ianguage. This description 3s verified using an evant driven simulator aftgr which it is passed through an optimi- zer which performs ?nntrol reordering and finds the essential data opcratorslregis- ters. This paper discusses a way of synthe- sizing the data part once the essential registers, operators and the data transfers between them are known. A canoni,-.al, para- m+trired structure is used to ma:> thest essential components into physical regis- ters, operators and interconnection paths. In the following section we describe the structure chosen for embedding the data part. In section III we describe a graph model for representing the data part and define the problem of mapping the data part into the structure. Section IV describes a heuristic algorithm for the problem stated 0738-100X/85/0381$01.00 0 1985 IEEE 22nd Design Automation Conference Paper 24.3 381