IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 1, JANUARY 2012 107 Effect of Stress-Induced Degradation in LDMOS 1/f Noise Characteristics M. I. Mahmud, Student Member, IEEE, Z. Çelik-Butler, Senior Member, IEEE, P. Hao, P. Srinivasan, Senior Member, IEEE, F. Hou, B. L. Amey, Member, IEEE, and S. Pendharkar, Member, IEEE Abstract—Low-frequency noise in double reduced-surface-field lateral-double-diffused-MOS devices has been measured, and the effect of dc stressing is analyzed. The noise components contribut- ing from the extended drain regions under the gate and field oxides were differentiated from the channel noise by a series of experi- mental and analytical techniques. The effect of voltage stressing on each noise component was investigated. Trapped-charge carrier fluctuations due to Si/SiO 2 interface traps in the overlap region in the extended drain as well as in the channel were found to be the dominant source of noise. The bulk resistance fluctuations in the extended drain region under the field oxide were found to be insignificant. High-voltage stressing caused an increase in the interface traps, thus increasing both the extended drain overlap resistance and the noise. Index Terms—High-voltage stressing, lateral double diffused MOS (LDMOS), reduced surface field (RESURF), 1/f noise. I. I NTRODUCTION A S THE requirements for voltage capability increase, lateral double diffused MOS (LDMOS) technology is gaining more attraction. The lateral geometry that makes it compatible with CMOS technology, however, is also respon- sible for high current densities and strong electric fields in the proximity of the Si/SiO 2 interface, resulting in hot carrier and other reliability issues [1]. Although extensive studies have been reported for LDMOS on its breakdown voltage, hot carrier reliability, safe operating area, and on-resistance degradation [1]–[4], there has been no comprehensive study on the effect of stressing on LDMOS low-frequency noise (LFN) charac- teristics. In this letter, we describe our experimental findings on the origin of fluctuations leading to LFN observed in the LDMOS drain voltage and the effect of dc stressing on the noise characteristics. LFN measurement is a nondestructive diagnostic method, which can be utilized to assess the gate- dielectric/silicon interface quality in CMOS, to characterize Manuscript received July 29, 2011; revised September 28, 2011; accepted October 3, 2011. Date of publication November 11, 2011; date of current version December 23, 2011. This work was supported in part by Semiconductor Research Corporation under Contract 2009-VJ-1959. The review of this letter was arranged by Editor S.-H. Ryu. M. I. Mahmud and Z. Çelik-Butler are with the Department of Electrical Engineering and the Nanotechnology Research and Teaching Facility, The University of Texas, Arlington, TX 76019 USA (e-mail: mdiqbal.mahmud@ mavs.uta.edu; zbutler@uta.edu). P. Hao, P. Srinivasan, F. Hou, B. L. Amey, and S. Pendharkar are with Texas Instruments Incorporated, Dallas, TX 75243 USA (e-mail: p-hao1@ti.com; psrinivasan@ti.com; fchou@ti.com; b-amey1@ti.com; s-pendharkar1@ ti.com). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2011.2171473 Fig. 1. Cross-sectional schematic for an LDMOS with all the resistance and noise components shown. S Vc , S V R ED GO , and S V R ED FO are the voltage fluctuations from channel, extended drain under the gate oxide, and under the field oxide, respectively. electromigration in metallizations and vias and to determine remaining device lifetime [5]. Recent studies on identification of degradation with stressing in LDMOS (Fig. 1) utilized relatively complex charge pumping and simulation-based tech- niques [2]–[4]. However, as the degradation of LDMOS is a function of bias voltages as well as the device process and layout parameters [3], the worst degradation condition and corresponding mechanism in each LDMOS device have to be investigated separately. Due to this, and partially due to the lack of a known universal degradation mechanism, no single nondestructive technique has emerged to date to assess the level of degradation in these devices. Our experimental results and analyses present a simple diagnostic methodology to identify the damage location in LDMOS induced due to (dc) voltage stressing. II. DEVICES AND EXPERIMENTS The details of experimental setup, procedure, and back- ground noise minimization were reported earlier [6]. The LDMOS devices contain an asymmetric extended drain con- sisting of a medium doped resistive region under the gate oxide (overlap region) and a lateral drift region under a bird’s beak shaped LOCOS field oxide to reduce electric field crowding (Fig. 1). The channel is formed in the highly doped p-body re- gion by the lateral diffusion difference (out-diffusion) between the source and the n-well. An n + buried layer is implanted in the lightly doped substrate to have double reduced surface field (RESURF) or floating-RESURF action [7]. Both the 30- and 0741-3106/$26.00 © 2011 IEEE