A Clock-fault Tolerant Architecture and Circuit for Reliable Nanoelectronics System Woon Tiong Ang, Hui Fei Rao, Changhong Yu*, Jilin Liu*, I-Chyn Wey + , An-Yeu (Andy) Wu + , Hong Zhao, and Jie Chen Electrical and Computer Engineering Department, University of Alberta, Edmonton, Canada *Electrical Engineering Department, Zhejiang University, China +Graduate Institute of Electronics Engineering, and Department of Electrical Engineering, National Taiwan University, Taiwan Corresponding Author: <woon@ualberta.ca> Abstract Due to discrepancies in manufacturing process and the probabilistic nature of quantum mechanical phenomenon, nanoelectronic devices cannot be made as reliable as current microelectronic devices. As a result, fault-tolerant architectures are a prerequisite to building reliable electronic systems from these unreliable nanoelectronic devices. One important design aspect of nanoelectronic architecture that demands attentive consideration is clock generation and distribution. Various defects and interference such as doping discrepancies, supply noise and cross-talks could lead to clock irregularity and malformed clock signals, thus resulting in faulty operations of sequential circuits. Generally, these errors are not readily amenable to efficient correction using error-correcting codes known to date. In this paper, we propose a novel fault-tolerant architecture for a parallel computation structure. The fault-tolerance capabilities built into this architecture allow for effective remedy against the deleterious effects of random clock abnormality and reduce the probability of computational errors. Central to the operation of the proposed fault-tolerant architecture is a novel clock-fault detection circuitry. In order to illustrate the fault- tolerance capability rendered by the detection circuitry, an error probability analysis is performed. Finally, a prototype CMOS design of this proposed circuit that consists of only 28 transistors and 2 capacitors is presented. Our simulation shows that with only a two-fold increase in hardware counts, the proposed architecture can gain significant fault-tolerance capability. Keywords: reliability, reliable electronics, nanoelectronics, fault tolerance 1. Introduction Hardware defect is an increasingly significant issue in the design and manufacture of modern integrated circuits. As the number of transistors on a chip increases to the giga scale, the economic cost required to maintain a defect-free hardware becomes astronomically prohibitive. Furthermore, the future of integrated circuits sees the use of novel technologies including single- electron tunneling (SET) [1] device, resonant tunneling transistors (RTT) [2], carbon nanotubes, and quantum cellular automata (QCA) [3]. Nano-electronics devices such as these, due to their quantum mechanical nature, cannot be expected to operate with perfect predictability at all times. Moreover, the environment in which the circuits are operated may further contribute to the unreliability of the circuit via the addition of noise and various forms of interference. Therefore, future nanoelectronic circuits should be designed to operate reliably in the presence of permanent hardware defects and transient signal faults. Various fault-tolerance techniques have been studied by physicists and computer scientists, the most notable of which includes Von Neumann [4]. Techniques such as N-tuple modular redundancy (NMR) [4], Triple Modular Redundancy (TMR) [5][6], NAND multiplexing [4] and others based on reconfigurable hardware [7][9] have been proposed in the literature. Nevertheless, little in-depth analysis has been devoted to the analysis or design of clock-fault handling structure suitable for nanoelectronics system. Error detection or correction for clock signal can be achieved using clock generators based on “quadricorrelator” [10], phase-locked loop (PLL) [11] and Costas Loop[12] architectures but these implementations are generally too hardware-demanding or area-consuming for liberal employment on an intrinsically error-prone nanoscale chip.. This paper proposes a fault-tolerant architecture for a computation unit suitable for employment in a reconfigurable, massively-parallel, and high-throughput computation system. Also proposed is a hardware-efficient clock-fault detection circuit which is central to the operation of the suggested architecture. The paper is organized as follows. In section 2, the proposed architecture of a clock-fault tolerant computation unit is presented. Section 3 features the proposed clock-fault detection circuit. A CMOS prototype design of the circuitry is demonstrated. 2. Architecture of a Clock-fault Tolerant Computation Unit 2.1 Proposed architecture of fault-tolerant computation unit ! ! " " # # Figure 1: Proposed architecture of a fault-tolerant computation unit employed in a 3 by 3 reconfigurable array. A generic reconfigurable system is shown in figure 1. This system comprises an arbitrary m by n array of our proposed fault-tolerant computation units but for illustration, we only display a 3 by 3