Replacement fin processing for III–V on Si: From FinFets to nanowires Niamh Waldron ⇑ , Clement Merckling, Lieve Teugels, Patrick Ong, Farid Sebaai, Kathy Barla, Nadine Collaert, Voon-Yew (Aaron) Thean imec, Kapeldreef 75, 3001 Leuven, Belgium article info Article history: Available online 23 October 2015 Keywords: III-V FinFet Gate-All-Around (GAA) Nanowire InGaAs MOS abstract In this paper we review the details and results of the replacement fin process technique used to success- fully demonstrate InGaAs based channel devices from FinFets to ultra scaled nanowires on 300 mm Si substrates. For FinFet devices a Mg p-type doping solution was developed to counteract the unintentional n-type doping of the InP buffer layer which resulted in high source-drain leakage. However, the perfor- mance of these devices is found to be limited by the Mg doping as the mobility is degraded. By switching to a GAA architecture the problem of source-leakage through the InP buffer is effectively eliminated and best devices with L G = 60 nm have a peak transconductance of 1030 lS/lm with a SS SAT of 125 mV/dec are achieved. A comparison of gate first to gate last processing highlights the importance of using a low thermal budget process to maintain the integrity of the InGaAs/high-K interface. Nanowires with a diameter of 6 nm were demonstrated to show quantization induced immunity to D it resulting in a SS SAT as low as 66 mV/dec for 85 nm L G devices. Ó 2015 Elsevier Ltd. All rights reserved. 1. Introduction III–V materials have long held promise as a high mobility chan- nel material for advanced scaling nodes. In recent years many excellent device results have been reported on 2 00 –4 00 lattice matched substrates [1–3]. However, in order to fully realize the potential of III–V as a VLSI compatible technology it is imperative that III–V can be demonstrated on a 300 mm Si platform. This is a considerable challenge; besides the 8% lattice mismatch between InP, In0. 53 Ga 0.47 As and Si, other considerations including cross-contamination and disparate thermal budgets have to be addressed. Several options have been considered to obtain high quality III–V layers on Si with low defect density: strain relaxed buffers [4–6], direct wafer bonding [7,8], epitaxial lateral over- growth [9,10], rapid melt growth [11] and the defect confinement technique [12,13]. In this work we leverage the defect confinement technique where defects are trapped at the STI sidewall in a replacement fin process. The replacement fin process offers a direct and flexible integration approach for a selection of channel materi- als, including the options for Ge-IIIV CMOS [14] together with wider band-gap options such as Si and SiGe devices fabricated from the same STI template. This allows for more options to tailor leakages, performance, and Vdd for a range of SOC requirements. We have already successfully demonstrated FinFet [15] and gate-all- around (GAA) devices [16] on 300 mm Si wafers using this tech- nique. The devices are integrated by process modules developed for a Si-IIIV hybrid 300 mm R&D pilot line, compatible for future CMOS high-volume manufacturing. In this paper we review the details of our replacement fin process and the device results obtained to date. 2. Device processing The replacement process begins with the generation of a shal- low trench isolation (STI) template on on-axis (0 0 1) 300 mm Si wafers. The processing of the STI template follows exactly the same route as would be used for standard Si FinFet devices. After the STI module the template consists of Si trenches in SiO. The pad oxide from the STI processing is removed by HF and the Si in the trenches is removed by Tetramethylammonium Hydroxide (TMAH) 5% at 80 °C. The TMAH etches the Si anisotropically so that the final etch profile results in {1 1 1} Si planes being revealed at the bottom of the trench thus creating a V-Groove. A III–V buffer layer can now be grown on the Si {111} planes (Fig. 1). For the InGaAs channel we choose InP for the buffer layer as In 0.53 Ga 0.47 As and InP are lat- tice matched. The concept of growing a lattice mismatched layer on Si in a narrow trench relies on the defect confinement technique which has previously been used to demonstrate high quality III–V layers on Si [17]. This technique uses high aspect ratio trenches (>2) to eliminate (1 1 1) oriented defects such as threading dislocations, http://dx.doi.org/10.1016/j.sse.2015.09.020 0038-1101/Ó 2015 Elsevier Ltd. All rights reserved. ⇑ Corresponding author. E-mail address: niamh.waldron@imec.be (N. Waldron). Solid-State Electronics 115 (2016) 81–91 Contents lists available at ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse