Energy-Efficient Near-Threshold Standard Cell Library for IoT Applications AbdelRahman Hesham 1 , Amin Nassar 1 , and Hassan Mostafa 1,2 1 Electronics and Communications Engineering Department, Cairo University, Egypt. 2 University of Science and technology, Nanotechnology and Nanoelectronics Program, Zewail City of Science and Technology, October Gardens, 6th of October, Giza 12578, Egypt. {a.heshamm@gmail.com, amin.nassar@yahoo.com, hmostafa@uwaterloo.ca} Abstract—In this paper, a low-energy minimum-area CMOS standard cell library suitable for IoT applications is proposed. Energy consumption reduction is achieved by operating the library in Near-Threshold Voltage (NTV) region, and by design- ing layout of cells at the minimum possible area for the used technology process. Body biasing technique is proposed to boost pMOS performance. Operating voltage and transistor sizing are also selected to achieve the minimum energy consumption while operating at the frequency range of 1MHz to 20MHz which is suitable for IoT applications. The proposed library was designed and characterized in UMC 130 nm CMOS technology process. The library was modeled to be used in synthesis tools. To prove the benefit for IoT applications, the library was benchmarked by implementing 3 cryptographic algorithms: ASCON, AEGIS-128, and AEZ. Synthesis results are showing that the three cores can operate at 18 MHz, 14 MHz, and 16 MHz respectively, while consuming 0.466 pJ, 3.006 pJ, and 5.064 pJ. Index Terms—CMOS digital integrated circuits, design methodology, near-threshold CMOS circuits, ultra-low power design, ultra-low energy, IoT, ASCON, AEGIS, AEZ I. I NTRODUCTION The Internet of Things (IoT) is a novel paradigm that is rapidly gaining ground in the scenario of modern wireless communication. This is resulting in a wide range of applica- tions touching every aspect of our life, like wearable devices, connected cars, and smart homes. Enablement of IoT spread is depending on the reliability of devices accessing it. Device reliability is based on: (1) computation power, (2) efficiency of energy consumption, and (3) security against possible threats. Computation power of IoT devices has been widely ex- plored in the literature [1]–[5], with a major interest in energy reduction techniques. These techniques have been explored and proposed at all design levels; namely circuit, logic, RTL, algorithm, and system levels. For IoT devices, most of energy saving is achieved by circuit-level solutions. One of the most growing topics in this area is the feasibility of voltage scaling to reduce energy consumption. Circuit design in subthreshold region has gained increasing interest to achieve low power requirements by operating the circuits at the Minimum Energy Point (MEP) [1]. The drawback of this MEP paradigm is the significant loss in performance [2]. To recover some of the performance loss while maintaining the power gains, Near- Threshold Voltage (NTV) operation was introduced [2]. It was shown that in NTV, energy savings can be in the order of 10X, with only a 10X degradation in performance, providing a much better energy/performance trade-off than subthreshold operation [3]. In addition to computation power and energy concerns in IoT applications, the possible threats deriving from widespread adoption of such a technology are stressed. As predicted by Cisco, there will be 50 billion IoT connected devices by 2020 [6]. Integration of such a tremendous number of devices into IoT potentially brings in a new concern, System Security. Thus, cryptography became one of the main approaches to secure and overcome attacks on user data. Significant research effort was done to provide algorithmic level cryptography solutions and to assess hardware implementation of these algorithms. In [7], ASIC implementation of 3 commonly used cryptography algorithms is conducted to check their suitability for IoT applications. Similarly, architectural solutions are proposed in [8] and used to implement co-processor suitable for Narrow-Band (NB) IoT devices. Also, in this direction and in 2012, the European Network of Excellence in Cryptology (ECRYPT) called for a new competition for authenticated ciphers: CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) [9]. Review of hard- ware implementation of CAESAR algorithms are presented in [10], [11]. The winning algorithms were announced in 2019, and they were covering 3 main areas of application: lightweight, high performance, and defense-in-depth. In this paper, 3 of these applications were explored for potential benefit in IoT devices. In this paper, a low-energy minimum-area standard cell library is proposed in UMC 130 nm process. Library is operating in NTV region at 350 mV supply. This supply was selected to achieve the minimum Power Delay Product (PDP) for the used process node. The minimum area is achieved by minimizing cell height and by utilizing Euler’s Path in design of each cell layout. A calculation method is proposed to get minimum cell height as a function of technology parameters. The Inverse Narrow Width Effect (INWE) was checked and utilized for library PPA gains. The proposed library is showing better energy and area measurements com- pared to other libraries surveyed. To show the gains from utilizing NTV operation, the library is benchmarked against a commercial library operating in Super-Threshold Voltage region to implement three of CAESAR finalists: ASCON [12], AEGIS-128 [13], and AEZ [14].