This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON ELECTRON DEVICES 1 Characterization of Monolithic InAlN/GaN NAND Logic Cell Supported by Circuit and Device Simulations Aleš Chvála , Lukáš Nagy, Juraj Marek , Juraj Priesol, Daniel Donoval, Member, IEEE , Michal Blaho, Dagmar Gregušová, Ján Kuzmík , and Alexander Šatka Abstract — In this brief, the monolithic integration of enhancement (E)-mode and depletion (D)-mode InAlN/GaN high-electron mobility transistors (HEMTs) is presented. The aim of this brief is to show the results of the designed NAND logic cell, which consists of both HEMTs integrated onto a single die. Large-signal models of dual-gate E-mode and D-mode HEMTs are proposed and calibrated by experi- mental results. We present well-calibrated electrophysical models for 2-D device simulations employing mixed- mode setup in Synopsys TCAD Sentaurus device. The mixed-mode approach interconnects dual-gate E-HEMT and D-HEMT to NAND logic cell circuit, which allows analysis and characterization of the device as the complex system. Good agreement between simulations and experimental results confirms the validity of the proposed models and simulation methodology. Index Terms— Circuit and device simulations, InAlN/GaN high-electron mobility transistor (HEMT), monolithic integration, NAND logic cell. I. I NTRODUCTION I N RECENT years, GaN-based high-electron mobility transistors (HEMTs) have attracted increasing attention for high-frequency, high-voltage, high-power, and high- temperature applications because of their excellent electronic properties, high-electron saturation velocity, and high break- down voltage [1], [2]. GaN transistors have a strong potential to gradually replace standard devices in microwave and power applications, switches, switching amplifiers, and in harsh environments (high temperatures, pressures, and radiation) Manuscript received February 14, 2018; revised March 23, 2018; accepted April 14, 2018. This work was supported in part by the Slovak Research and Development Agency under Contract APVV-15-0673, in part by the Ministry of Education, Science, Research and Sport of Slovakia under Grant VEGA 1/0491/15, and in part by University Science Park STU under Grant ITMS 26240220084. The review of this brief was arranged by Editor S. Rajan. (Corresponding author: Aleš Chvála.) A. Chvála, L. Nagy, J. Marek, J. Priesol, D. Donoval, and A. Šatka are with the Institute of Electronics and Photonics, Slovak University of Technology in Bratislava, 812 19 Bratislava, Slovakia (e-mail: ales.chvala@stuba.sk; lukas.nagy@stuba.sk; juraj.marek@stuba.sk; juraj.priesol@stuba.sk; daniel.donoval@stuba.sk; alexander.satka@ stuba.sk). M. Blaho, D. Gregušová, and J. Kuzmík are with the Institute of Electrical Engineering, Slovak Academy of Sciences, 841 04 Bratislava, Slovakia (e-mail: michal.blaho@savba.sk; dagmar.gregusova@ savba.sk; jan.kuzmik@savba.sk). Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2018.2828464 commonly used in industrial environments, mobile devices, and extreme power electronics. However, there are still a lot of areas to be investigated in order to extract and utilize the favorable GaN material properties. Among them, the most important is to develop a new, GaN specific technology, structure design, and characterization techniques. The dual-gate device technology, based on cascade config- uration, has already been utilized to obtain the small parasitic effects, faster switching, higher output power, and higher breakdown voltage without adding to the device size or design complexity [3], [4]. From the structure of a dual-gate device, the second gate provides an extra depletion region that allows for significant simplification of the device design and/or improvement in the associated gate-to-drain capacitance and output resistance [5]. The promising properties of the dual-gate device can be utilized for the design of NAND logic cells or the implementation of analog functions such as multiplication and signal mixing. For the successful design of digital circuits comprised inverters, NAND and/or OR logic cells, and their complements, it is necessary to design structures integrating enhancement (E)-mode and depletion (D)-mode transistors on the same chip. In this brief, the design, fabrication process, and character- ization of the InAlN/GaN monolithic digital circuit forming NAND logic cell are proposed. The InAlN/GaN structure was selected due to higher polarization-induced charge and lattice- matched barrier providing better performance and scalability compared to the AlGaN/GaN structure [2]. The proposed NAND logic cell monolithically integrates dual-gate E-mode and D-mode transistors on a single substrate. Self-aligned metal–insulator–semiconductor gate is used for the reduction of the gate leakage. Modified large-signal models of dual-gate E-mode and D-mode HEMTs are proposed. Characterization of NAND logic cell is supported by 2-D device modeling and simulation. Mixed-mode setup supported in Sentaurus device simulator allows interconnection of both transistor types to the NAND logic cell circuit [6] to perform complete device modeling and simulations. A well-calibrated circuit and device models of both structures are experimentally validated. II. STRUCTURE DESCRIPTION The proposed InAlN/GaN NAND logic circuit cell is com- prised dual-gate E-HEMT and D-HEMT [Fig. 1(a)]. DHEMT is employed as a constant current source. We could also 0018-9383 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.